Trigger driver

HAL_TRIG. More...

Data Structures
struct	trig_init_t
	trigger init parameter More...
struct	trig_hdr_t
	trigger handler parameter More...
struct	trig_output_cmd_t
	trigger direct output command parameter More...
struct	trig_set_tmr_cmd_t
	trigger set timer command parameter More...
struct	trig_wait_tmr_cmd_t
	trigger wait timer command parameter More...
struct	trig_reg_rd_cmp_cmd_t
	trigger register read and compare command parameter More...
struct	trig_reg_wr_cmd_t
	trigger register write command parameter More...
struct	trig_reg_rw_cmd_t
	trigger register read and write command parameter More...
struct	trig_reg_cp_cmd_t
	trigger register copy command parameter More...
struct	trig_reg_mask_cp_cmd_t
	trigger register copy with mask command parameter More...
struct	trig_sig_t
	trigger condition parameter More...

Macros
#define	TRIG_HIGH_PRI_Q_MAX_TRIG_ID   8
	Max trigger id for high priority queue.
#define	TRIG_MID_PRI_Q_MAX_TRIG_ID   8
	Max trigger id for middle priority queue.
#define	TRIG_LOW_PRI_Q_MAX_TRIG_ID   16
	Max trigger id for low priority queue.
#define	TRIG_HIGH_PRI_Q_CMD_START_ADDR   TRIG_HIGH_PRI_Q_MAX_TRIG_ID
	Command start address for high priority queue.
#define	TRIG_MID_PRI_Q_CMD_START_ADDR   TRIG_MID_PRI_Q_MAX_TRIG_ID
	Command start address for middle priority queue.
#define	TRIG_HP_INTR_CMD_COMPLETED   0x1
	High priority queue command completed interrupt.
#define	TRIG_HP_INTR_QUEUE_OV   0x2
	High priority queue overflow interrupt.
#define	TRIG_HP_INTR_QUEUE_EMPTY   0x4
	High priority queue empty interrupt.
#define	TRIG_HP_INTR_INVALID_CMD   0x8
	High priority queue invalid command interrupt.
#define	TRIG_HP_INTR_TIMER_TMO   0x10
	High priority queue timer timeout interrupt.
#define	TRIG_HP_INTR_TIMER_DONE   0x20
	High priority queue timer done interrupt.
#define	TRIG_HP_INTR_READ_COMPARE_FAIL   0x40
	High priority queue read compare fail reach maximum number allowed interrupt.
#define	TRIG_MP_INTR_CMD_COMPLETED   0x100
	Middle priority queue command completed interrupt.
#define	TRIG_MP_INTR_QUEUE_OV   0x200
	Middle priority queue overflow interrupt.
#define	TRIG_MP_INTR_QUEUE_EMPTY   0x400
	Middle priority queue empty interrupt.
#define	TRIG_MP_INTR_INVALID_CMD   0x800
	Middle priority queue invalid command interrupt.
#define	TRIG_MP_INTR_TIMER_TMO   0x1000
	Middle priority queue timer timeout interrupt.
#define	TRIG_MP_INTR_TIMER_DONE   0x2000
	Middle priority queue timer done interrupt.
#define	TRIG_MP_INTR_READ_COMPARE_FAIL   0x4000
	Middle priority queue read compare fail reach maximum number allowed interrupt.
#define	TRIG_LP_INTR_CMD_COMPLETED   0x10000
	Low priority queue command completed interrupt.
#define	TRIG_LP_INTR_QUEUE_OV   0x20000
	Low priority queue overflow interrupt.
#define	TRIG_LP_INTR_QUEUE_EMPTY   0x40000
	Low priority queue empty interrupt.
#define	TRIG_LP_INTR_INVALID_CMD   0x80000
	Low priority queue invalid command interrupt.
#define	TRIG_LP_INTR_TIMER_TMO   0x100000
	Low priority queue timer timeout interrupt.
#define	TRIG_LP_INTR_TIMER_DONE   0x200000
	Low priority queue timer done interrupt.
#define	TRIG_LP_INTR_READ_COMPARE_FAIL   0x400000
	Low priority queue read compare fail reach maximum number allowed interrupt.
#define	TRIG_HP_INTR_CMD_START   0x1
	High priority queue command start interrupt.
#define	TRIG_HP_INTR_CMD_DONE   0x2
	High priority queue command done interrupt.
#define	TRIG_MP_INTR_CMD_START   0x10
	Middle priority queue command start interrupt.
#define	TRIG_MP_INTR_CMD_DONE   0x20
	Middle priority queue command done interrupt.
#define	TRIG_LP_INTR_CMD_START   0x100
	Low priority queue command start interrupt.
#define	TRIG_LP_INTR_CMD_DONE   0x200
	Low priority queue command done interrupt.

Enumerations
enum	trig_err { TRIG_ERR_OK = 0, TRIG_ERR_INVALID_PARAM = -1, TRIG_ERR_MEM_OVERFLOW = -2, TRIG_ERR_MUTEX = -4 }
	trigger error code More...
enum	trig_queue { TRIG_HP_QUEUE = 0, TRIG_MP_QUEUE =1, TRIG_LP_QUEUE = 2, TRIG_MAX_QUEUE = 3 }
	trigger queue More...
enum	trig_odc_idx {   TIRG_ODC_GPIO_OUTPUT_BASE_IDX = 0, TRIG_ODC_GPIO_OEN_BASE_IDX = 39, TRIG_ODC_TRX_REG_APB_MUX = 78, TRIG_ODC_TRX_SEQ_APB_MUX = 79,   TRIG_ODC_SHM_APB_MUX = 80, TRIG_ODC_PWM_APB_MUX = 81, TRIG_ODC_TRIG_APB_MUX = 82, TRIG_ODC_GLOBAL_REG_APB_MUX = 83,   TRIG_ODC_GLOBAL2_REG_APB_MUX = 84, TRIG_ODC_ADC_APB_MUX = 85, TRIG_ODC_TMR_APB_MUX = 86, TRIG_ODC_I2C1_APB_MUX = 87,   TRIG_ODC_I2C0_APB_MUX = 88, TRIG_ODC_UART1_APB_MUX = 89, TRIG_ODC_UART0_APB_MUX = 90, TRIG_ODC_SSPI_APB_MUX = 91,   TRIG_ODC_MSPI1_APB_MUX = 92, TRIG_ODC_MSPI0_APB_MUX = 93, TRIG_ODC_TMR_ADD_APB_MUX = 94, TRIG_ODC_SNAPSHOT_AON_TMR3 = 95,   TRIG_ODC_EN_IPMAC = 98, TRIG_ODC_SUSPEND_IPMAC = 99, TRIG_ODC_BB_FORCE_TX_EN = 100, TRIG_ODC_BB_FORCE_RX_EN = 101,   TRIG_ODC_RX_IQ_CAP_EN = 102, TRIG_ODC_SNAPSHOT_AON_TMR0 = 103, TRIG_ODC_SNAPSHOT_AON_TMR1 = 104, TRIG_ODC_SNAPSHOT_AON_TMR2 = 105,   TRIG_ODC_SNAPSHOT_BLE_BB_CNT = 106, TRIG_ODC_SNAPSHOT_IPMAC_CNT = 107, TRIG_ODC_SNAPSHOT_TMR0 = 108, TRIG_ODC_SNAPSHOT_TMR1 = 109,   TRIG_ODC_SNAPSHOT_TMR2 = 110, TRIG_ODC_SNAPSHOT_TMR3 = 111, TRIG_ODC_SNAPSHOT_TMR4 = 112, TRIG_ODC_SNAPSHOT_TMR5 = 113,   TRIG_ODC_SNAPSHOT_IPMAC_TS = 114, TRIG_ODC_SNAPSHOT_BLE_TS = 115, TRIG_ODC_SNAPSHOT_SYSTICK = 116, TRIG_ODC_SNAPSHOT_HQ_TMR = 117,   TRIG_ODC_SNAPSHOT_MQ_TMR = 118, TRIG_ODC_SNAPSHOT_LQ_TMR = 119, TRIG_ODC_SNAPSHOT_FR_IPMAC_CNT = 120, TRIG_ODC_SNAPSHOT_TMR6 = 121,   TRIG_ODC_SNAPSHOT_TMR7 = 122, TRIG_ODC_SNAPSHOT_TMR8 = 123, TRIG_ODC_SNAPSHOT_TMR9 = 124, TRIG_ODC_SNAPSHOT_AON_WDT_TMR = 125,   TRIG_ODC_MAX, TRIG_ODC_UNUSED_IDX = 0x3FF }
	trigger output direct control index More...
enum	trig_sig_idx {   TIRG_SIG_GPIO_INPUT_BASE_ID = 0, TRIG_SIG_GPIO_OUTPUT_BASE_ID = 39, TRIG_SIG_GPIO_IE_OE_BASE_ID = 78, TRIG_SIG_TMR0_EMIT8 = 117,   TRIG_SIG_TMR0_EMIT9 = 118, TRIG_SIG_TMR1_EMIT0 = 119, TRIG_SIG_TMR1_EMIT1 = 120, TRIG_SIG_TMR1_EMIT2 = 121,   TRIG_SIG_TMR1_EMIT3 = 122, TRIG_SIG_TMR1_EMIT4 = 123, TRIG_SIG_TMR1_EMIT5 = 124, TRIG_SIG_TMR1_EMIT6 = 125,   TRIG_SIG_TMR1_EMIT7 = 126, TRIG_SIG_TMR1_EMIT8 = 127, TRIG_SIG_TMR1_EMIT9 = 128, TRIG_SIG_SEQ_RX_EN_GPIO = 129,   TRIG_SIG_SEQ_TX_EN_GPIOA = 130, TRIG_SIG_SEQ_TX_EN_GPIOB = 131, TRIG_SIG_SEQ_GP_TOGGLE = 132, TRIG_SIG_TMR6_IRQ = 133,   TRIG_SIG_TMR7_IRQ = 134, TRIG_SIG_TMR8_IRQ = 135, TRIG_SIG_TMR9_IRQ = 136, TRIG_SIG_TMR6_EMIT0 = 137,   TRIG_SIG_TMR6_EMIT1 = 138, TRIG_SIG_TMR6_EMIT2 = 139, TRIG_SIG_TMR6_EMIT3 = 140, TRIG_SIG_TMR6_EMIT4 = 141,   TRIG_SIG_TMR6_EMIT5 = 142, TRIG_SIG_TMR6_EMIT6 = 143, TRIG_SIG_TMR6_EMIT7 = 144, TRIG_SIG_TMR6_EMIT8 = 145,   TRIG_SIG_TMR6_EMIT9 = 146, TRIG_SIG_IPMAC_FREERUN_IRQ0 = 147, TRIG_SIG_IPMAC_FREERUN_IRQ1 = 148, TRIG_SIG_IPMAC_SLV_IN_SYNC = 149,   TRIG_SIG_IPMAC_SLV_SYNC_MISS = 150, TRIG_SIG_IPMAC_SCAN_START = 151, TRIG_SIG_IPMAC_SCAN_CH_DONE = 152, TRIG_SIG_IPMAC_SCAN_ALL_CH_DONE = 153,   TRIG_SIG_IPMAC_FREERUN_US_TICK = 154, TRIG_SIG_WDT_RST = 156, TRIG_SIG_WDT_IRQ = 157, TRIG_SIG_TX_EN = 158,   TRIG_SIG_RX_EN = 159, TRIG_SIG_SYNC_IN_WIN = 160, TRIG_SIG_SYNC_OUT_WIN = 161, TRIG_SIG_2M_PHY = 162,   TRIG_SIG_PA_EN = 163, TRIG_SIG_FE_TX_EN = 164, TRIG_SIG_FE_RX_EN = 165, TRIG_SIG_WLAN_TX = 166,   TRIG_SIG_WLAN_RX = 167, TRIG_SIG_MDM_SYNC_FOUND = 168, TRIG_SIG_IN_SYNC_SRCH = 169, TRIG_SIG_AGC_TOO_LOW = 170,   TRIG_SIG_AGC_TOO_HIGH = 171, TRIG_SIG_BLE_EVENT_START = 172, TRIG_SIG_IPMAC_SF_START = 173, TRIG_SIG_IPMAC_RESP_RX_DONE = 174,   TRIG_SIG_IPMAC_BCN_RX_DONE = 175, TRIG_SIG_IPMAC_RESP_TX_DONE = 176, TRIG_SIG_IPMAC_BCN_TX_DONE = 177, TRIG_SIG_BLE_TX_SYNC = 178,   TRIG_SIG_BLE_TX_PRE = 179, TRIG_SIG_IPMAC_TX_SYNC = 180, TRIG_SIG_IPMAC_TX_PRE = 181, TRIG_SIG_OSC_EN = 182,   TRIG_SIG_BLE_DEEP_SLEEP = 183, TRIG_SIG_BLE_RX_CRC_FAIL = 184, TRIG_SIG_BLE_RX_CRC_PASS = 185, TRIG_SIG_BLE_IRQ0 = 186,   TRIG_SIG_BLE_IRQ1 = 187, TRIG_SIG_BLE_EVENT_DONE = 188, TRIG_SIG_IPMAC_SUSPEND = 189, TRIG_SIG_CPU_WFI = 190,   TRIG_SIG_CPU_HALT = 191, TRIG_SIG_CPU_LOCKUP = 192, TRIG_SIG_CPU_RST = 193, TRIG_SIG_PA_TARGET = 194,   TRIG_SIG_PA_OFF = 195, TRIG_SIG_BOD_OUT = 196, TRIG_SIG_BOD2_OUT = 197, TRIG_SIG_XO_RDY = 198,   TRIG_SIG_XO_EN = 199, TRIG_SIG_AON_TMR0_IRQ = 200, TRIG_SIG_AON_TMR1_IRQ = 201, TRIG_SIG_AON_TMR2_IRQ = 202,   TRIG_SIG_AON_TMR3_IRQ = 203, TRIG_SIG_AON_WDT_TMR_IRQ = 204, TIRG_SIG_AON_SYSTICK_STOP = 205, TRIG_SIG_AON_SYSTICK_START = 206,   TRIG_SIG_AON_SYSTICK_IRQ = 207, TRIG_SIG_AON_SYSTICK_EMIT = 208, TRIG_SIG_WAKEUP_SRC_RDY = 209, TRIG_SIG_TMR0_IRQ = 210,   TRIG_SIG_TMR1_IRQ = 211, TRIG_SIG_TMR2_IRQ = 212, TRIG_SIG_TMR3_IRQ = 213, TRIG_SIG_TMR4_IRQ = 214,   TRIG_SIG_TMR5_IRQ = 215, TRIG_SIG_AON_TMR2_EMIT0 = 216, TRIG_SIG_AON_TMR2_EMIT1 = 217, TRIG_SIG_AON_TMR2_CAP0 = 218,   TRIG_SIG_AON_TMR2_CAP1 = 219, TRIG_SIG_TMR0_EMIT0 = 220, TRIG_SIG_TMR0_EMIT1 = 221, TRIG_SIG_TMR0_EMIT2 = 222,   TRIG_SIG_TMR0_EMIT3 = 223, TRIG_SIG_TMR0_EMIT4 = 224, TRIG_SIG_TMR0_EMIT5 = 225, TRIG_SIG_TMR0_EMIT6 = 226,   TRIG_SIG_TMR0_EMIT7 = 227, TRIG_SIG_CPLL_RST = 228, TRIG_SIG_CPLL_EN = 229, TRIG_SIG_CPLL_LOCKED = 230,   TRIG_SIG_MPLL_RST = 231, TRIG_SIG_MPLL_EN = 232, TRIG_SIG_MPLL_LOCKED = 233, TRIG_SIG_SYSTICK = 234,   TRIG_SIG_SYSTICK_IRQ = 235, TRIG_SIG_CPU_IRQ0 = 236, TRIG_SIG_CPU_IRQ1 = 237, TRIG_SIG_CPU_IRQ2 = 238,   TRIG_SIG_CPU_IRQ3 = 239, TRIG_SIG_CPU_IRQ4 = 240, TRIG_SIG_CPU_IRQ5 = 241, TRIG_SIG_CPU_IRQ6 = 242,   TRIG_SIG_CPU_IRQ7 = 243, TRIG_SIG_BLE_CLKN_MATCH0 = 244, TRIG_SIG_BLE_CLKN_MATCH1 = 245, TRIG_SIG_SYSTEM_BUS_HIT = 249,   TRIG_SIG_DATA_BUS_HIT = 250, TRIG_SIG_PC_HIT = 251, TRIG_SIG_SW0 = 252, TRIG_SIG_SW1 = 253,   TRIG_SIG_SW2 = 254, TRIG_SIG_DISABLE = 255 }
	trigger signal index More...
enum	trig_ble_irq_t {   TRIG_BLE_IRQ_SW = 0, TRIG_BLE_IRQ_FINE = 1, TRIG_BLE_IRQ_GROSS = 2, TRIG_BLE_IRQ_TS = 3,   TRIG_BLE_IRQ_ERR = 4, TRIG_BLE_IRQ_CRYPT = 5, TRIG_BLE_IRQ_START = 6, TRIG_BLE_IRQ_END = 7,   TRIG_BLE_IRQ_SKIP = 8, TRIG_BLE_IRQ_SLEEP = 9, TRIG_BLE_IRQ_TX = 10, TRIG_BLE_IRQ_RX = 11,   TRIG_BLE_IRQ_HALF_SLOT = 12, TRIG_BLE_IRQ_EVT_FSM_TIMEOUT = 13, TRIG_BLE_IRQ_CLKN_MISS = 15, TRIG_BLE_IRQ_CLKN_MATCH = 19,   TRIG_BLE_IRQ_EVT_TIMEOUT = 20, TRIG_BLE_IRQ_FSM_TIMEOUT = 21 }
	BLE IRQ signal. More...
enum	trig_timer_val_t { TRIG_TMR_CMD = 0, TRIG_TMR_REG = 1 }
	trigger timer value More...
enum	trig_reg_cp_len_t { TRIG_REG_1_BYTE = 0, TRIG_REG_2_BYTES = 1 }
	trigger register copy length More...
enum	trig_reg_bus_t { TRIG_REG_AHB = 0, TRIG_REG_APB = 1 }
	trigger register access bus More...
enum	trig_reg_comp_cond_t { TRIG_REG_EQUAL = 0, TRIG_REG_NOT_EQUAL = 1, TRIG_REG_LARGER = 2, TRIG_REG_LESS = 3 }
	trigger register compare condition More...
enum	trig_apb_mux_t {   TRIG_APB_MSPI0 = 0, TRIG_APB_MSPI1 = 1, TRIG_APB_SSPI = 2, TRIG_APB_UART0 = 3,   TRIG_APB_UART1 = 4, TRIG_APB_I2C0 = 5, TRIG_APB_I2C1 = 6, TRIG_APB_TMR = 7,   TRIG_APB_ADC = 8, TRIG_APB_GLOBAL = 9, TRIG_APB_TRIG = 10, TRIG_APB_PWM = 11,   TRIG_APB_SHM = 12, TRIG_APB_TRX_SEQ = 13, TRIG_APB_TRX = 14, TRIG_APB_GLOBAL2 = 15,   TRIG_APB_TMR_ADD = 16 }
	trigger apb bus mux More...

Functions
int	hal_trig_open (trig_init_t *init)
	Open Trig device. More...
void	hal_trig_close (void)
	Close Trig device. More...
int	hal_trig_set_mem_addr (int queue, uint32_t mem_addr)
	Set share mem word address. More...
int	hal_trig_queue_enable (int queue)
	Enable trig queue. More...
int	hal_trig_queue_disable (int queue)
	Disable trig queue. More...
int	hal_trig_wr_header (int queue, int trig_id, trig_hdr_t *hdr)
	Write trig header. More...
int	hal_trig_output_cmd (int queue, uint32_t addr_offset, trig_output_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger output direct control command. More...
int	hal_trig_set_tmr_cmd (int queue, uint32_t addr_offset, trig_set_tmr_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger set timer command. More...
int	hal_trig_wait_tmr_cmd (int queue, uint32_t addr_offset, trig_wait_tmr_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger wait timer command. More...
int	hal_trig_reg_rd_cmp_cmd (int queue, uint32_t addr_offset, trig_reg_rd_cmp_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger register read and compare command. More...
int	hal_trig_reg_wr_cmd (int queue, uint32_t addr_offset, trig_reg_wr_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger register write command. More...
int	hal_trig_reg_rw_cmd (int queue, uint32_t addr_offset, trig_reg_rw_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger register read and write command. More...
int	hal_trig_reg_copy_cmd (int queue, uint32_t addr_offset, trig_reg_cp_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger register copy and write command. More...
int	hal_trig_reg_mask_copy_cmd (int queue, uint32_t addr_offset, trig_reg_mask_cp_cmd_t *cmd, uint32_t *cmd_addr_oft)
	Write trigger register copy with mask command. More...
int	hal_trig_set_sig (int queue, int trig_id, trig_sig_t *sig)
	Set trig signal. More...
int	hal_trig_odc_gpio_output_en (int port, int pin, int en)
	Enable GPIO output for trigger ODC output. More...
int	hal_trig_odc_gpio_oen_en (int port, int pin, int en)
	Enable GPIO OE for trigger ODC output. More...
int	hal_trig_odc_gpio_output_idx (int port, int pin)
	Get GPIO output index for trigger ODC index. More...
int	hal_trig_odc_gpio_oen_idx (int port, int pin)
	Get GPIO OE index for trigger ODC index. More...
int	hal_trig_sig_gpio_input_idx (int port, int pin)
	Get GPIO input index for trigger signal. More...
int	hal_trig_sig_gpio_ie_oe_idx (int port, int pin)
	Get GPIO ie or oe index for trigger signal. Use hal_trig_sig_gpio_ie_oe to select ie/oe. More...
int	hal_trig_sig_gpio_output_idx (int port, int pin)
	Get GPIO output index for trigger signal. More...
int	hal_trig_null_cmd (int queue, uint32_t addr_offset, uint32_t *cmd_addr_oft)
	Null command. More...
uint32_t	hal_trig_curr_cmd_addr (int queue)
	Get current command address. This address is used for next command. It is word address offset. More...
int	hal_trig_sig_gpio_ie_oe (int port, int pin, int oe)
	Set trigger signal for GPIO ie/oe. More...
int	hal_trig_sig_ble_irq (int idx, uint8_t irq_signal)
	Set BLE IRQ signal for trigger signal TRIG_SIG_BLE_IRQ0 and TRIG_SIG_BLE_IRQ1. More...
int	hal_trig_sig_cpu_irq (int idx, uint8_t irq_num)
	Set CPU IRQ signal for trigger signal TRIG_SIG_CPU_IRQ0 ~ TRIG_SIG_CPU_IRQ7. More...
int	hal_trig_tmr_init_tick (int queue, uint32_t init_val)
	Set trigger timer initial tick value to register. More...
int	hal_trig_tmr_reload_tick (int queue, uint32_t reload_val)
	Set trigger timer reload tick value to register. More...
int	hal_trig_apb_mux (int peripheral, int bus_sel)
	Set peripheral apb bus mux for trigger. More...
void	hal_trig_resume (void)
	Manually resume trigger after wake up. Should set auto_resume to 0 when open trigger. More...
int	hal_trig_intr_sig (int queue, int trig_sig)
	Set trigger signal for interrupt status 1, TRIG_HP_INTR_CMD_START. More...

Detailed Description

HAL_TRIG.

Enumeration Type Documentation

trig_apb_mux_t

enum trig_apb_mux_t

trigger apb bus mux

Enumerator
TRIG_APB_MSPI0	Master SPI0.
TRIG_APB_MSPI1	Master SPI1.
TRIG_APB_SSPI	Slave SPI.
TRIG_APB_UART0	UART0.
TRIG_APB_UART1	UART1.
TRIG_APB_I2C0	I2C0.
TRIG_APB_I2C1	I2C1.
TRIG_APB_TMR	Timer 0 ~ timer 5.
TRIG_APB_ADC	ADC.
TRIG_APB_GLOBAL	Global register.
TRIG_APB_TRIG	Trigger handler register.
TRIG_APB_PWM	PWM.
TRIG_APB_SHM	Share memory register.
TRIG_APB_TRX_SEQ	TRX sequencer register.
TRIG_APB_TRX	TRX register.
TRIG_APB_GLOBAL2	Global2 register.
TRIG_APB_TMR_ADD	Timer additional register(timer6 ~ timer9)

trig_ble_irq_t

enum trig_ble_irq_t

BLE IRQ signal.

Enumerator
TRIG_BLE_IRQ_SW	Software IRQ.
TRIG_BLE_IRQ_FINE	Fine target timer IRQ.
TRIG_BLE_IRQ_GROSS	Gross target timer IRQ.
TRIG_BLE_IRQ_TS	Timestamp target IRQ.
TRIG_BLE_IRQ_ERR	Error IRQ.
TRIG_BLE_IRQ_CRYPT	Cryption IRQ.
TRIG_BLE_IRQ_START	Start of envent IRQ.
TRIG_BLE_IRQ_END	End of event IRQ.
TRIG_BLE_IRQ_SKIP	Event Skipped IRQ.
TRIG_BLE_IRQ_SLEEP	End of sleep IRQ.
TRIG_BLE_IRQ_TX	End of TX IRQ.
TRIG_BLE_IRQ_RX	End of RX IRQ.
TRIG_BLE_IRQ_HALF_SLOT	Half slot IRQ.
TRIG_BLE_IRQ_EVT_FSM_TIMEOUT	Event scheduler main FSM timeout IRQ.
TRIG_BLE_IRQ_CLKN_MISS	Event FSM CLKN miss IRQ.
TRIG_BLE_IRQ_CLKN_MATCH	CLKN count match IRQ.
TRIG_BLE_IRQ_EVT_TIMEOUT	Event timeout IRQ.
TRIG_BLE_IRQ_FSM_TIMEOUT	Scheduler FSM timeout IRQ.

trig_err

enum trig_err

trigger error code

Enumerator
TRIG_ERR_OK	No error.
TRIG_ERR_INVALID_PARAM	Invalid parameter.
TRIG_ERR_MEM_OVERFLOW	Memory overflow.
TRIG_ERR_MUTEX	Mutex error.

trig_odc_idx

enum trig_odc_idx

trigger output direct control index

Enumerator
TIRG_ODC_GPIO_OUTPUT_BASE_IDX	GPIO output base index, hal_trig_odc_gpio_output_idx.
TRIG_ODC_GPIO_OEN_BASE_IDX	GPIO oen base index, hal_trig_odc_gpio_oen_idx.
TRIG_ODC_TRX_REG_APB_MUX	TRX register APB mux.
TRIG_ODC_TRX_SEQ_APB_MUX	TRX sequencer register APB MUX.
TRIG_ODC_SHM_APB_MUX	Share memory register APB mux.
TRIG_ODC_PWM_APB_MUX	PWM APB mux.
TRIG_ODC_TRIG_APB_MUX	Trigger handler APB mux.
TRIG_ODC_GLOBAL_REG_APB_MUX	Global register APB mux.
TRIG_ODC_GLOBAL2_REG_APB_MUX	Global2 register APB mux.
TRIG_ODC_ADC_APB_MUX	ADC register APB mux.
TRIG_ODC_TMR_APB_MUX	Timer register APB mux.
TRIG_ODC_I2C1_APB_MUX	I2C1 register APB mux.
TRIG_ODC_I2C0_APB_MUX	I2C0 register APB mux.
TRIG_ODC_UART1_APB_MUX	UART1 register APB mux.
TRIG_ODC_UART0_APB_MUX	UART0 register APB mux.
TRIG_ODC_SSPI_APB_MUX	Slave SPI APB mux.
TRIG_ODC_MSPI1_APB_MUX	Master SPI1 register APB mux.
TRIG_ODC_MSPI0_APB_MUX	Master SPI0 register APB mux.
TRIG_ODC_TMR_ADD_APB_MUX	Timer additional register(timer6 ~ timer9) APB mux.
TRIG_ODC_SNAPSHOT_AON_TMR3	Snapshot AON timer 3.
TRIG_ODC_EN_IPMAC	Enable IPMAC.
TRIG_ODC_SUSPEND_IPMAC	Suspend IPMAC.
TRIG_ODC_BB_FORCE_TX_EN	Force baseband Tx EN.
TRIG_ODC_BB_FORCE_RX_EN	Force baseband Rx EN.
TRIG_ODC_RX_IQ_CAP_EN	Enable RX I/Q capture.
TRIG_ODC_SNAPSHOT_AON_TMR0	Snapshot AON timer 0.
TRIG_ODC_SNAPSHOT_AON_TMR1	Snapshot AON timer 1.
TRIG_ODC_SNAPSHOT_AON_TMR2	Snapshot AON timer 2.
TRIG_ODC_SNAPSHOT_BLE_BB_CNT	Snapshot BLE baseband counter(CLKN and fine)
TRIG_ODC_SNAPSHOT_IPMAC_CNT	Snapshot IPMAC counter(superframe, duration, and fine)
TRIG_ODC_SNAPSHOT_TMR0	Snapshot timer 0.
TRIG_ODC_SNAPSHOT_TMR1	Snapshot timer 1.
TRIG_ODC_SNAPSHOT_TMR2	Snapshot timer 2.
TRIG_ODC_SNAPSHOT_TMR3	Snapshot timer 3.
TRIG_ODC_SNAPSHOT_TMR4	Snapshot timer 4.
TRIG_ODC_SNAPSHOT_TMR5	Snapshot timer 5.
TRIG_ODC_SNAPSHOT_IPMAC_TS	Snapshot IPMAC timestamp counter(superframe + 24bit free running counter)
TRIG_ODC_SNAPSHOT_BLE_TS	Snapshot BLE timestamp counter(27 bits)
TRIG_ODC_SNAPSHOT_SYSTICK	Snapshot system tick counter (coarse and fine)
TRIG_ODC_SNAPSHOT_HQ_TMR	Snapshot trigger handler high priority queue timer.
TRIG_ODC_SNAPSHOT_MQ_TMR	Snapshot trigger handler middle priority queue timer.
TRIG_ODC_SNAPSHOT_LQ_TMR	Snapshot trigger handler low priority queue timer.
TRIG_ODC_SNAPSHOT_FR_IPMAC_CNT	Snapshot IPMAC free running counter(superframe, duration, and fine)
TRIG_ODC_SNAPSHOT_TMR6	Snapshot timer 6(additional timer 0)
TRIG_ODC_SNAPSHOT_TMR7	Snapshot timer 7(additional timer 1)
TRIG_ODC_SNAPSHOT_TMR8	Snapshot timer 8(additional timer 2)
TRIG_ODC_SNAPSHOT_TMR9	Snapshot timer 9(additional timer 3)
TRIG_ODC_SNAPSHOT_AON_WDT_TMR	Snapshot AON watch dog timer.
TRIG_ODC_MAX	Max trigger ODC index.
TRIG_ODC_UNUSED_IDX	unused index

trig_queue

enum trig_queue

trigger queue

Enumerator
TRIG_HP_QUEUE	High priority queue.
TRIG_MP_QUEUE	Middle priority queue.
TRIG_LP_QUEUE	Low priority queue.
TRIG_MAX_QUEUE	Max queue.

trig_reg_bus_t

enum trig_reg_bus_t

trigger register access bus

Enumerator
TRIG_REG_AHB	Use AHB bus.
TRIG_REG_APB	Use APB bus.

trig_reg_comp_cond_t

enum trig_reg_comp_cond_t

trigger register compare condition

Enumerator
TRIG_REG_EQUAL	Equal.
TRIG_REG_NOT_EQUAL	Not equal.
TRIG_REG_LARGER	Larger.
TRIG_REG_LESS	Less.

trig_reg_cp_len_t

enum trig_reg_cp_len_t

trigger register copy length

Enumerator
TRIG_REG_1_BYTE	Copy 1 byte.
TRIG_REG_2_BYTES	Copy 2 bytes.

trig_sig_idx

enum trig_sig_idx

trigger signal index

Enumerator
TIRG_SIG_GPIO_INPUT_BASE_ID	GPIO input base index, hal_trig_sig_gpio_input_idx.
TRIG_SIG_GPIO_OUTPUT_BASE_ID	GPIO output base index, hal_trig_sig_gpio_output_idx.
TRIG_SIG_GPIO_IE_OE_BASE_ID	GPIO ie/oe base index. To set oe or ie, hal_trig_sig_gpio_ie_oe.
TRIG_SIG_TMR0_EMIT8	Timer 0 emit 8 signal.
TRIG_SIG_TMR0_EMIT9	Timer 0 emit 9 signal.
TRIG_SIG_TMR1_EMIT0	Timer 1 emit 0 signal.
TRIG_SIG_TMR1_EMIT1	Timer 1 emit 1 signal.
TRIG_SIG_TMR1_EMIT2	Timer 1 emit 2 signal.
TRIG_SIG_TMR1_EMIT3	Timer 1 emit 3 signal.
TRIG_SIG_TMR1_EMIT4	Timer 1 emit 4 signal.
TRIG_SIG_TMR1_EMIT5	Timer 1 emit 5 signal.
TRIG_SIG_TMR1_EMIT6	Timer 1 emit 6 signal.
TRIG_SIG_TMR1_EMIT7	Timer 1 emit 7 signal.
TRIG_SIG_TMR1_EMIT8	Timer 1 emit 8 signal.
TRIG_SIG_TMR1_EMIT9	Timer 1 emit 9 signal.
TRIG_SIG_SEQ_RX_EN_GPIO	TRX sequencer RX enable GPIO.
TRIG_SIG_SEQ_TX_EN_GPIOA	TRX sequencer TX enable GPIO A.
TRIG_SIG_SEQ_TX_EN_GPIOB	TRX sequencer TX enable GPIO B.
TRIG_SIG_SEQ_GP_TOGGLE	TRX sequencer general-purpose toggle signal, check register 0x46a04034 to 0x46a040FC.
TRIG_SIG_TMR6_IRQ	Timer 6(addtional timer 0) timeout IRQ.
TRIG_SIG_TMR7_IRQ	Timer 7(addtional timer 1) timeout IRQ.
TRIG_SIG_TMR8_IRQ	Timer 8(addtional timer 2) timeout IRQ.
TRIG_SIG_TMR9_IRQ	Timer 9(addtional timer 3) timeout IRQ.
TRIG_SIG_TMR6_EMIT0	Timer 6(addtional timer 0) emit 0 signal.
TRIG_SIG_TMR6_EMIT1	Timer 6(addtional timer 0) emit 1 signal.
TRIG_SIG_TMR6_EMIT2	Timer 6(addtional timer 0) emit 2 signal.
TRIG_SIG_TMR6_EMIT3	Timer 6(addtional timer 0) emit 3 signal.
TRIG_SIG_TMR6_EMIT4	Timer 6(addtional timer 0) emit 4 signal.
TRIG_SIG_TMR6_EMIT5	Timer 6(addtional timer 0) emit 5 signal.
TRIG_SIG_TMR6_EMIT6	Timer 6(addtional timer 0) emit 6 signal.
TRIG_SIG_TMR6_EMIT7	Timer 6(addtional timer 0) emit 7 signal.
TRIG_SIG_TMR6_EMIT8	Timer 6(addtional timer 0) emit 8 signal.
TRIG_SIG_TMR6_EMIT9	Timer 6(addtional timer 0) emit 9 signal.
TRIG_SIG_IPMAC_FREERUN_IRQ0	IPMAC free running IRQ 0.
TRIG_SIG_IPMAC_FREERUN_IRQ1	IPMAC free running IRQ 1.
TRIG_SIG_IPMAC_SLV_IN_SYNC	IPMAC slave in sync.
TRIG_SIG_IPMAC_SLV_SYNC_MISS	IPMAC slave sync miss.
TRIG_SIG_IPMAC_SCAN_START	IPMAC background scan start.
TRIG_SIG_IPMAC_SCAN_CH_DONE	IPMAC background scan channel done.
TRIG_SIG_IPMAC_SCAN_ALL_CH_DONE	IPMAC background scan all channel done.
TRIG_SIG_IPMAC_FREERUN_US_TICK	IPMAC free running us tick.
TRIG_SIG_WDT_RST	PD1 Watch dog reset.
TRIG_SIG_WDT_IRQ	PD1 Watch dog timeout IRQ.
TRIG_SIG_TX_EN	BLE TX enable.
TRIG_SIG_RX_EN	BLE RX enable.
TRIG_SIG_SYNC_IN_WIN	Sync found signal in sync window.
TRIG_SIG_SYNC_OUT_WIN	Sync found signal outside of sync window.
TRIG_SIG_2M_PHY	2M data rate
TRIG_SIG_PA_EN	PA 2.4G enable.
TRIG_SIG_FE_TX_EN	Front end TX enable.
TRIG_SIG_FE_RX_EN	Front end RX enable.
TRIG_SIG_WLAN_TX	External input WLAN TX signal.
TRIG_SIG_WLAN_RX	External input WLAN RX signal.
TRIG_SIG_MDM_SYNC_FOUND	Modem sync found.
TRIG_SIG_IN_SYNC_SRCH	BLE or IPMAC in sync search mode.
TRIG_SIG_AGC_TOO_LOW	AGC too low.
TRIG_SIG_AGC_TOO_HIGH	AGC too high.
TRIG_SIG_BLE_EVENT_START	BLE event start.
TRIG_SIG_IPMAC_SF_START	IPMAC frame start.
TRIG_SIG_IPMAC_RESP_RX_DONE	IPMAC master rx done.
TRIG_SIG_IPMAC_BCN_RX_DONE	IPMAC slave rx done.
TRIG_SIG_IPMAC_RESP_TX_DONE	IPMAC slave tx done.
TRIG_SIG_IPMAC_BCN_TX_DONE	IPMAC master tx done.
TRIG_SIG_BLE_TX_SYNC	Start of Sync sequence Tx in BLE baseband.
TRIG_SIG_BLE_TX_PRE	Start of preamble Tx in BLE baseband.
TRIG_SIG_IPMAC_TX_SYNC	Start of Sync sequence Tx in IPMAC.
TRIG_SIG_IPMAC_TX_PRE	Start of preamble Tx in IPMAC.
TRIG_SIG_OSC_EN	Input osc_en from PD0.
TRIG_SIG_BLE_DEEP_SLEEP	BLE deep sleep enable.
TRIG_SIG_BLE_RX_CRC_FAIL	BLE RX packet with CRC fail.
TRIG_SIG_BLE_RX_CRC_PASS	BLE RX packet with CRC pass.
TRIG_SIG_BLE_IRQ0	BLE IRQ signal 0, set irq signal with hal_trig_sig_ble_irq.
TRIG_SIG_BLE_IRQ1	BLE IRQ signal 1, set irq signal with hal_trig_sig_ble_irq.
TRIG_SIG_BLE_EVENT_DONE	BLE event done.
TRIG_SIG_IPMAC_SUSPEND	IPMAC in suspend.
TRIG_SIG_CPU_WFI	CPU in WFI.
TRIG_SIG_CPU_HALT	CPU in halt.
TRIG_SIG_CPU_LOCKUP	CPU in lockup.
TRIG_SIG_CPU_RST	CPU reset.
TRIG_SIG_PA_TARGET	PA reached target gain.
TRIG_SIG_PA_OFF	PA off.
TRIG_SIG_BOD_OUT	Input BOD out from PMU.
TRIG_SIG_BOD2_OUT	Input BOD2 out from PMU.
TRIG_SIG_XO_RDY	XO ready from PD0.
TRIG_SIG_XO_EN	XO enable from PD0.
TRIG_SIG_AON_TMR0_IRQ	AON timer 0 timeout IRQ.
TRIG_SIG_AON_TMR1_IRQ	AON timer 1 timeout IRQ.
TRIG_SIG_AON_TMR2_IRQ	AON timer 2 timeout IRQ.
TRIG_SIG_AON_TMR3_IRQ	AON timer 3 timeout IRQ.
TRIG_SIG_AON_WDT_TMR_IRQ	AON watch dog timer timeout IRQ.
TIRG_SIG_AON_SYSTICK_STOP	System tick aon timer stop ack signal.
TRIG_SIG_AON_SYSTICK_START	System tick aon timer start ack signal.
TRIG_SIG_AON_SYSTICK_IRQ	System tick aon timer timeout IRQ.
TRIG_SIG_AON_SYSTICK_EMIT	System tick aon timer emit signal.
TRIG_SIG_WAKEUP_SRC_RDY	Wake up source ready signal.
TRIG_SIG_TMR0_IRQ	Timer 0 timeout IRQ.
TRIG_SIG_TMR1_IRQ	Timer 1 timeout IRQ.
TRIG_SIG_TMR2_IRQ	Timer 2 timeout IRQ.
TRIG_SIG_TMR3_IRQ	Timer 3 timeout IRQ.
TRIG_SIG_TMR4_IRQ	Timer 4 timeout IRQ.
TRIG_SIG_TMR5_IRQ	Timer 5 timeout IRQ.
TRIG_SIG_AON_TMR2_EMIT0	AON timer 2 emit 0 signal.
TRIG_SIG_AON_TMR2_EMIT1	AON timer 2 emit 1 signal.
TRIG_SIG_AON_TMR2_CAP0	AON timer 2 capture signal 0 captured.
TRIG_SIG_AON_TMR2_CAP1	AON timer 2 capture signal 1 captured.
TRIG_SIG_TMR0_EMIT0	Timer 0 emit 0 signal.
TRIG_SIG_TMR0_EMIT1	Timer 0 emit 1 signal.
TRIG_SIG_TMR0_EMIT2	Timer 0 emit 2 signal.
TRIG_SIG_TMR0_EMIT3	Timer 0 emit 3 signal.
TRIG_SIG_TMR0_EMIT4	Timer 0 emit 4 signal.
TRIG_SIG_TMR0_EMIT5	Timer 0 emit 5 signal.
TRIG_SIG_TMR0_EMIT6	Timer 0 emit 6 signal.
TRIG_SIG_TMR0_EMIT7	Timer 0 emit 7 signal.
TRIG_SIG_CPLL_RST	CPLL reset.
TRIG_SIG_CPLL_EN	CPLL enable.
TRIG_SIG_CPLL_LOCKED	CPLL locked.
TRIG_SIG_MPLL_RST	MPLL reset.
TRIG_SIG_MPLL_EN	MPLL enable.
TRIG_SIG_MPLL_LOCKED	MPLL locked.
TRIG_SIG_SYSTICK	System tick signal.
TRIG_SIG_SYSTICK_IRQ	System tick block IRQ(53), check register 0x4410C380.
TRIG_SIG_CPU_IRQ0	CPU IRQ signal 0, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ1	CPU IRQ signal 1, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ2	CPU IRQ signal 2, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ3	CPU IRQ signal 3, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ4	CPU IRQ signal 4, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ5	CPU IRQ signal 5, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ6	CPU IRQ signal 6, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_CPU_IRQ7	CPU IRQ signal 7, set irq number with hal_trig_sig_cpu_irq.
TRIG_SIG_BLE_CLKN_MATCH0	BLE CLKN matched(value 0)
TRIG_SIG_BLE_CLKN_MATCH1	BLE CLKN matched(value 1)
TRIG_SIG_SYSTEM_BUS_HIT	CM4 system bus address match with an address specified in a global control register.
TRIG_SIG_DATA_BUS_HIT	CM4 data bus address match with an address specified in a global control register.
TRIG_SIG_PC_HIT	CM4 program counter matched with an address specified in a global control register.
TRIG_SIG_SW0	Software trigger 0.
TRIG_SIG_SW1	Software trigger 1.
TRIG_SIG_SW2	Software trigger 2.
TRIG_SIG_DISABLE	Disable.

trig_timer_val_t

enum trig_timer_val_t

trigger timer value

Enumerator
TRIG_TMR_CMD	Trigger timer use command initial/reload value.
TRIG_TMR_REG	Trigger timer use register initial/reload value.

Function Documentation

hal_trig_apb_mux()

int hal_trig_apb_mux	(	int	peripheral,
		int	bus_sel
	)

Set peripheral apb bus mux for trigger.

Parameters

[in]	peripheral	Peripheral, enum trig_apb_mux_t
[in]	bus_sel	0: AHB bus, 1:APB bus, enum trig_reg_bus_t

Returns

See also

enum trig_err for the possible return code.

hal_trig_close()

void hal_trig_close

(

void

)

Close Trig device.

---

Returns

none

---

hal_trig_curr_cmd_addr()

uint32_t hal_trig_curr_cmd_addr

(

int

queue

)

Get current command address. This address is used for next command. It is word address offset.

Parameters

[in]

queue

Queue id, enum trig_queue.

Returns

Current command address.

hal_trig_intr_sig()

int hal_trig_intr_sig	(	int	queue,
		int	trig_sig
	)

Set trigger signal for interrupt status 1, TRIG_HP_INTR_CMD_START.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	trig_sig	Trigger signal, trig_sig_idx

Returns

None.

hal_trig_null_cmd()

int hal_trig_null_cmd	(	int	queue,
		uint32_t	addr_offset,
		uint32_t *	cmd_addr_oft
	)

Null command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[out]	cmd_len	Command length, used for calculate next command address

Returns

See also

enum trig_err for the possible return code.

hal_trig_odc_gpio_oen_en()

int hal_trig_odc_gpio_oen_en	(	int	port,
		int	pin,
		int	en
	)

Enable GPIO OE for trigger ODC output.

If enable GPIO OE for trigger ODC, can't use register to control GPIO. The ODC ouput is low active, that means when OE is 1, the ODC output is 0.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin
[in]	en	1: enable, 0:disable

Returns

See also

enum trig_err for the possible return code.

hal_trig_odc_gpio_oen_idx()

int hal_trig_odc_gpio_oen_idx	(	int	port,
		int	pin
	)

Get GPIO OE index for trigger ODC index.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin

Returns

GPIO OE trigger ODC index, enum trig_odc_idx .

hal_trig_odc_gpio_output_en()

int hal_trig_odc_gpio_output_en	(	int	port,
		int	pin,
		int	en
	)

Enable GPIO output for trigger ODC output.

If enable GPIO output for trigger ODC, can't use register to control GPIO.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin
[in]	en	1: enable, 0:disable

Returns

See also

enum trig_err for the possible return code.

hal_trig_odc_gpio_output_idx()

int hal_trig_odc_gpio_output_idx	(	int	port,
		int	pin
	)

Get GPIO output index for trigger ODC index.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin

Returns

GPIO output trigger ODC index, enum trig_odc_idx .

hal_trig_open()

int hal_trig_open

(

trig_init_t *

init

)

Open Trig device.

---

Parameters

[in]

init

Trig device init parameter, trig_init_t.

Returns

See also

enum trig_err for the possible return code.

---

hal_trig_output_cmd()

int hal_trig_output_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_output_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger output direct control command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Trig output direct control command, trig_output_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_queue_disable()

int hal_trig_queue_disable

(

int

queue

)

Disable trig queue.

Parameters

[in]

queue

Queue id, enum trig_queue.

Returns

See also

enum trig_err for the possible return code.

hal_trig_queue_enable()

int hal_trig_queue_enable

(

int

queue

)

Enable trig queue.

Parameters

[in]

queue

Queue id, enum trig_queue.

Returns

See also

enum trig_err for the possible return code.

hal_trig_reg_copy_cmd()

int hal_trig_reg_copy_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_reg_cp_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger register copy and write command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Copy command, trig_reg_cp_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_reg_mask_copy_cmd()

int hal_trig_reg_mask_copy_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_reg_mask_cp_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger register copy with mask command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Copy command, trig_reg_mask_cp_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_reg_rd_cmp_cmd()

int hal_trig_reg_rd_cmp_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_reg_rd_cmp_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger register read and compare command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Read and compare command, trig_reg_rd_cmp_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_reg_rw_cmd()

int hal_trig_reg_rw_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_reg_rw_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger register read and write command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Read and write command, trig_reg_rw_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_reg_wr_cmd()

int hal_trig_reg_wr_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_reg_wr_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger register write command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Write command, trig_reg_wr_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_resume()

void hal_trig_resume

(

void

)

Manually resume trigger after wake up. Should set auto_resume to 0 when open trigger.

Returns

None.

hal_trig_set_mem_addr()

int hal_trig_set_mem_addr	(	int	queue,
		uint32_t	mem_addr
	)

Set share mem word address.

Parameters

[in]	queue	Queue id, enum trig_queue. This funtion is not available for high priority queue.
[in]	mem_addr	Share mem address. This is word address offset. Default middle priority queue mem address is 0x0, low priority queue address is 0x200.

Returns

See also

enum trig_err for the possible return code.

hal_trig_set_sig()

int hal_trig_set_sig	(	int	queue,
		int	trig_id,
		trig_sig_t *	sig
	)

Set trig signal.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	trig_id	Trig id.
[in]	sig	Trig signal, trig_sig_t.

Returns

See also

enum trig_err for the possible return code.

hal_trig_set_tmr_cmd()

int hal_trig_set_tmr_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_set_tmr_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger set timer command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Set timer command, trig_wait_tmr_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_sig_ble_irq()

int hal_trig_sig_ble_irq	(	int	idx,
		uint8_t	irq_signal
	)

Set BLE IRQ signal for trigger signal TRIG_SIG_BLE_IRQ0 and TRIG_SIG_BLE_IRQ1.

Parameters

[in]	idx	Trigger signal index, should be TRIG_SIG_BLE_IRQ0 or TRIG_SIG_BLE_IRQ1
[in]	irq_signal	BLE IRQ signal,

See also

enum trig_ble_irq_t

Returns

See also

enum trig_err for the possible return code.

hal_trig_sig_cpu_irq()

int hal_trig_sig_cpu_irq	(	int	idx,
		uint8_t	irq_num
	)

Set CPU IRQ signal for trigger signal TRIG_SIG_CPU_IRQ0 ~ TRIG_SIG_CPU_IRQ7.

Parameters

[in]	idx	Trigger signal index, should be TRIG_SIG_CPU_IRQ0 ~ TRIG_SIG_CPU_IRQ7.
[in]	irq_signal	CPU IRQ signal,

See also

IRQn_Type

Returns

See also

enum trig_err for the possible return code.

hal_trig_sig_gpio_ie_oe()

int hal_trig_sig_gpio_ie_oe	(	int	port,
		int	pin,
		int	oe
	)

Set trigger signal for GPIO ie/oe.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin
[in]	oe	1: oe, 0:ie. Default is ie.

Returns

See also

enum trig_err for the possible return code.

hal_trig_sig_gpio_ie_oe_idx()

int hal_trig_sig_gpio_ie_oe_idx	(	int	port,
		int	pin
	)

Get GPIO ie or oe index for trigger signal. Use hal_trig_sig_gpio_ie_oe to select ie/oe.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin

Returns

GPIO ie or oe trigger signal, enum trig_sig_idx .

hal_trig_sig_gpio_input_idx()

int hal_trig_sig_gpio_input_idx	(	int	port,
		int	pin
	)

Get GPIO input index for trigger signal.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin

Returns

GPIO input trigger signal, enum trig_sig_idx .

hal_trig_sig_gpio_output_idx()

int hal_trig_sig_gpio_output_idx	(	int	port,
		int	pin
	)

Get GPIO output index for trigger signal.

Parameters

[in]	port	GPIO port
[in]	pin	GPIO pin

Returns

GPIO output trigger signal, enum trig_sig_idx .

hal_trig_tmr_init_tick()

int hal_trig_tmr_init_tick	(	int	queue,
		uint32_t	init_val
	)

Set trigger timer initial tick value to register.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	init_val	Initial tick

Returns

See also

enum trig_err for the possible return code.

hal_trig_tmr_reload_tick()

int hal_trig_tmr_reload_tick	(	int	queue,
		uint32_t	reload_val
	)

Set trigger timer reload tick value to register.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	reload_val	reload tick

Returns

See also

enum trig_err for the possible return code.

hal_trig_wait_tmr_cmd()

int hal_trig_wait_tmr_cmd	(	int	queue,
		uint32_t	addr_offset,
		trig_wait_tmr_cmd_t *	cmd,
		uint32_t *	cmd_addr_oft
	)

Write trigger wait timer command.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	addr_offset	Command word address offset(not byte address).
[in]	cmd	Set timer command, trig_wait_tmr_cmd_t.
[out]	cmd_addr_oft	Command address offset. This is word address offset.

Returns

See also

enum trig_err for the possible return code.

hal_trig_wr_header()

int hal_trig_wr_header	(	int	queue,
		int	trig_id,
		trig_hdr_t *	hdr
	)

Write trig header.

Parameters

[in]	queue	Queue id, enum trig_queue.
[in]	trig_id	Trig id.
[in]	hdr	Trig header, trig_hdr_t.

Returns

See also

enum trig_err for the possible return code.