hal_trig.h

#ifndef HAL_TRIG_HDL_H
#define HAL_TRIG_HDL_H
#include <stdint.h>
#include "in_mmap.h"
#include "in_compile.h"
#if !CFG_NO_OS
#include "cmsis_os.h"
#endif

#define TRIG_ODC_MAX_OUTPUT_NUM 5
#define TRIG_MAX_ADDR_OFT 512


#define TRIG_SET_TMR_CMD_LEN 1
#define TRIG_WAIT_TMR_CMD_LEN 1
#define TRIG_REG_RD_COMP_CMD_LEN 4
#define TRIG_REG_WR_CMD_LEN 3
#define TRIG_REG_RD_MODIFY_WR_CMD_LEN 4
#define TRIG_REG_CP_CMD_LEN 3
#define TRIG_REG_MASK_CP_CMD_LEN 4
#define TRIG_OUTPUT_CMD_LEN 2
#define TRIG_NULL_CMD_LEN 1

#define TRIG_HIGH_PRI_Q_MAX_TRIG_ID 8 
#define TRIG_MID_PRI_Q_MAX_TRIG_ID 8 
#define TRIG_LOW_PRI_Q_MAX_TRIG_ID 16 
#define TRIG_HIGH_PRI_Q_CMD_START_ADDR TRIG_HIGH_PRI_Q_MAX_TRIG_ID 
#define TRIG_MID_PRI_Q_CMD_START_ADDR TRIG_MID_PRI_Q_MAX_TRIG_ID 
#define TRIG_LOW_PRI_Q_CMD_START_ADDR TRIG_LOW_PRI_Q_MAX_TRIG_ID 


/* Interrupt status 0 */
#define TRIG_HP_INTR_CMD_COMPLETED      0x1 
#define TRIG_HP_INTR_QUEUE_OV                   0x2  
#define TRIG_HP_INTR_QUEUE_EMPTY                0x4 
#define TRIG_HP_INTR_INVALID_CMD                0x8 
#define TRIG_HP_INTR_TIMER_TMO                  0x10 
#define TRIG_HP_INTR_TIMER_DONE             0x20    
#define TRIG_HP_INTR_READ_COMPARE_FAIL  0x40    

#define TRIG_MP_INTR_CMD_COMPLETED      0x100   
#define TRIG_MP_INTR_QUEUE_OV                   0x200 
#define TRIG_MP_INTR_QUEUE_EMPTY                0x400 
#define TRIG_MP_INTR_INVALID_CMD                0x800 
#define TRIG_MP_INTR_TIMER_TMO                  0x1000 
#define TRIG_MP_INTR_TIMER_DONE             0x2000 
#define TRIG_MP_INTR_READ_COMPARE_FAIL  0x4000 

#define TRIG_LP_INTR_CMD_COMPLETED      0x10000 
#define TRIG_LP_INTR_QUEUE_OV                   0x20000 
#define TRIG_LP_INTR_QUEUE_EMPTY                0x40000 
#define TRIG_LP_INTR_INVALID_CMD                0x80000 
#define TRIG_LP_INTR_TIMER_TMO                  0x100000 
#define TRIG_LP_INTR_TIMER_DONE             0x200000 
#define TRIG_LP_INTR_READ_COMPARE_FAIL  0x400000 

/* Interrupt status 1 */
#define TRIG_HP_INTR_CMD_START 0x1 
#define TRIG_HP_INTR_CMD_DONE 0x2 
#define TRIG_MP_INTR_CMD_START 0x10 
#define TRIG_MP_INTR_CMD_DONE 0x20 
#define TRIG_LP_INTR_CMD_START 0x100 
#define TRIG_LP_INTR_CMD_DONE 0x200 


enum trig_err {
    TRIG_ERR_OK = 0, 
    TRIG_ERR_INVALID_PARAM = -1, 
    TRIG_ERR_MEM_OVERFLOW = -2, 
    TRIG_ERR_MUTEX = -4, 
};

enum trig_queue {
    TRIG_HP_QUEUE = 0, 
    TRIG_MP_QUEUE =1,   
    TRIG_LP_QUEUE = 2,  
    TRIG_MAX_QUEUE = 3, 
};

enum trig_odc_idx {
    TIRG_ODC_GPIO_OUTPUT_BASE_IDX = 0, 
    TRIG_ODC_GPIO_OEN_BASE_IDX = 39, 
    TRIG_ODC_TRX_REG_APB_MUX = 78, 
    TRIG_ODC_TRX_SEQ_APB_MUX = 79, 
    TRIG_ODC_SHM_APB_MUX = 80, 
    TRIG_ODC_PWM_APB_MUX = 81, 
    TRIG_ODC_TRIG_APB_MUX = 82, 
    TRIG_ODC_GLOBAL_REG_APB_MUX = 83, 
    TRIG_ODC_GLOBAL2_REG_APB_MUX = 84, 
    TRIG_ODC_ADC_APB_MUX = 85, 
    TRIG_ODC_TMR_APB_MUX = 86, 
    TRIG_ODC_I2C1_APB_MUX = 87, 
    TRIG_ODC_I2C0_APB_MUX = 88, 
    TRIG_ODC_UART1_APB_MUX = 89, 
    TRIG_ODC_UART0_APB_MUX = 90, 
    TRIG_ODC_SSPI_APB_MUX = 91, 
    TRIG_ODC_MSPI1_APB_MUX = 92, 
    TRIG_ODC_MSPI0_APB_MUX = 93, 
    TRIG_ODC_TMR_ADD_APB_MUX = 94, 
    TRIG_ODC_SNAPSHOT_AON_TMR3 = 95, 
    TRIG_ODC_EN_IPMAC = 98, 
    TRIG_ODC_SUSPEND_IPMAC = 99, 
    TRIG_ODC_BB_FORCE_TX_EN = 100, 
    TRIG_ODC_BB_FORCE_RX_EN = 101, 
    TRIG_ODC_RX_IQ_CAP_EN = 102, 
    TRIG_ODC_SNAPSHOT_AON_TMR0 = 103, 
    TRIG_ODC_SNAPSHOT_AON_TMR1 = 104, 
    TRIG_ODC_SNAPSHOT_AON_TMR2 = 105, 
    TRIG_ODC_SNAPSHOT_BLE_BB_CNT = 106, 
    TRIG_ODC_SNAPSHOT_IPMAC_CNT = 107, 
    TRIG_ODC_SNAPSHOT_TMR0 = 108, 
    TRIG_ODC_SNAPSHOT_TMR1 = 109, 
    TRIG_ODC_SNAPSHOT_TMR2 = 110, 
    TRIG_ODC_SNAPSHOT_TMR3 = 111, 
    TRIG_ODC_SNAPSHOT_TMR4 = 112, 
    TRIG_ODC_SNAPSHOT_TMR5 = 113, 
    TRIG_ODC_SNAPSHOT_IPMAC_TS = 114, 
    TRIG_ODC_SNAPSHOT_BLE_TS = 115, 
    TRIG_ODC_SNAPSHOT_SYSTICK = 116, 
    TRIG_ODC_SNAPSHOT_HQ_TMR = 117, 
    TRIG_ODC_SNAPSHOT_MQ_TMR = 118, 
    TRIG_ODC_SNAPSHOT_LQ_TMR = 119, 
    TRIG_ODC_SNAPSHOT_FR_IPMAC_CNT = 120, 
    TRIG_ODC_SNAPSHOT_TMR6 = 121, 
    TRIG_ODC_SNAPSHOT_TMR7 = 122, 
    TRIG_ODC_SNAPSHOT_TMR8 = 123, 
    TRIG_ODC_SNAPSHOT_TMR9 = 124, 
    TRIG_ODC_SNAPSHOT_AON_WDT_TMR = 125, 
    TRIG_ODC_MAX, 
    TRIG_ODC_UNUSED_IDX = 0x3FF, 
};

enum trig_sig_idx {
    TIRG_SIG_GPIO_INPUT_BASE_ID = 0, 
    TRIG_SIG_GPIO_OUTPUT_BASE_ID = 39, 
    TRIG_SIG_GPIO_IE_OE_BASE_ID = 78, 
    TRIG_SIG_TMR0_EMIT8 = 117, 
    TRIG_SIG_TMR0_EMIT9 = 118, 
    TRIG_SIG_TMR1_EMIT0 = 119, 
    TRIG_SIG_TMR1_EMIT1 = 120, 
    TRIG_SIG_TMR1_EMIT2 = 121, 
    TRIG_SIG_TMR1_EMIT3 = 122, 
    TRIG_SIG_TMR1_EMIT4 = 123, 
    TRIG_SIG_TMR1_EMIT5 = 124, 
    TRIG_SIG_TMR1_EMIT6 = 125, 
    TRIG_SIG_TMR1_EMIT7 = 126, 
    TRIG_SIG_TMR1_EMIT8 = 127, 
    TRIG_SIG_TMR1_EMIT9 = 128, 
    TRIG_SIG_SEQ_RX_EN_GPIO = 129, 
    TRIG_SIG_SEQ_TX_EN_GPIOA = 130, 
    TRIG_SIG_SEQ_TX_EN_GPIOB = 131, 
    TRIG_SIG_SEQ_GP_TOGGLE = 132, 
    TRIG_SIG_TMR6_IRQ = 133, 
    TRIG_SIG_TMR7_IRQ = 134, 
    TRIG_SIG_TMR8_IRQ = 135, 
    TRIG_SIG_TMR9_IRQ = 136, 
    TRIG_SIG_TMR6_EMIT0 = 137, 
    TRIG_SIG_TMR6_EMIT1 = 138, 
    TRIG_SIG_TMR6_EMIT2 = 139, 
    TRIG_SIG_TMR6_EMIT3 = 140, 
    TRIG_SIG_TMR6_EMIT4 = 141, 
    TRIG_SIG_TMR6_EMIT5 = 142, 
    TRIG_SIG_TMR6_EMIT6 = 143, 
    TRIG_SIG_TMR6_EMIT7 = 144, 
    TRIG_SIG_TMR6_EMIT8 = 145, 
    TRIG_SIG_TMR6_EMIT9 = 146, 
    TRIG_SIG_IPMAC_FREERUN_IRQ0 = 147, 
    TRIG_SIG_IPMAC_FREERUN_IRQ1 = 148, 
    TRIG_SIG_IPMAC_SLV_IN_SYNC = 149, 
    TRIG_SIG_IPMAC_SLV_SYNC_MISS = 150, 
    TRIG_SIG_IPMAC_SCAN_START = 151, 
    TRIG_SIG_IPMAC_SCAN_CH_DONE = 152, 
    TRIG_SIG_IPMAC_SCAN_ALL_CH_DONE = 153, 
    TRIG_SIG_IPMAC_FREERUN_US_TICK = 154, 
    TRIG_SIG_WDT_RST = 156, 
    TRIG_SIG_WDT_IRQ = 157, 
    TRIG_SIG_TX_EN = 158, 
    TRIG_SIG_RX_EN = 159, 
    TRIG_SIG_SYNC_IN_WIN = 160, 
    TRIG_SIG_SYNC_OUT_WIN = 161, 
    TRIG_SIG_2M_PHY = 162, 
    TRIG_SIG_PA_EN = 163, 
    TRIG_SIG_FE_TX_EN = 164, 
    TRIG_SIG_FE_RX_EN = 165, 
    TRIG_SIG_WLAN_TX = 166, 
    TRIG_SIG_WLAN_RX = 167, 
    TRIG_SIG_MDM_SYNC_FOUND = 168, 
    TRIG_SIG_IN_SYNC_SRCH = 169, 
    TRIG_SIG_AGC_TOO_LOW = 170, 
    TRIG_SIG_AGC_TOO_HIGH = 171, 
    TRIG_SIG_BLE_EVENT_START = 172, 
    TRIG_SIG_IPMAC_SF_START = 173, 
    TRIG_SIG_IPMAC_RESP_RX_DONE = 174, 
    TRIG_SIG_IPMAC_BCN_RX_DONE = 175, 
    TRIG_SIG_IPMAC_RESP_TX_DONE = 176, 
    TRIG_SIG_IPMAC_BCN_TX_DONE = 177, 
    TRIG_SIG_BLE_TX_SYNC = 178, 
    TRIG_SIG_BLE_TX_PRE = 179, 
    TRIG_SIG_IPMAC_TX_SYNC = 180, 
    TRIG_SIG_IPMAC_TX_PRE = 181, 
    TRIG_SIG_OSC_EN = 182, 
    TRIG_SIG_BLE_DEEP_SLEEP = 183, 
    TRIG_SIG_BLE_RX_CRC_FAIL = 184, 
    TRIG_SIG_BLE_RX_CRC_PASS = 185, 
    TRIG_SIG_BLE_IRQ0 = 186, 
    TRIG_SIG_BLE_IRQ1 = 187, 
    TRIG_SIG_BLE_EVENT_DONE = 188, 
    TRIG_SIG_IPMAC_SUSPEND = 189, 
    TRIG_SIG_CPU_WFI = 190, 
    TRIG_SIG_CPU_HALT = 191, 
    TRIG_SIG_CPU_LOCKUP = 192, 
    TRIG_SIG_CPU_RST = 193, 
    TRIG_SIG_PA_TARGET = 194, 
    TRIG_SIG_PA_OFF = 195, 
    TRIG_SIG_BOD_OUT = 196, 
    TRIG_SIG_BOD2_OUT = 197, 
    TRIG_SIG_XO_RDY = 198, 
    TRIG_SIG_XO_EN = 199, 
    TRIG_SIG_AON_TMR0_IRQ = 200, 
    TRIG_SIG_AON_TMR1_IRQ = 201, 
    TRIG_SIG_AON_TMR2_IRQ = 202, 
    TRIG_SIG_AON_TMR3_IRQ = 203, 
    TRIG_SIG_AON_WDT_TMR_IRQ = 204, 
    TIRG_SIG_AON_SYSTICK_STOP = 205, 
    TRIG_SIG_AON_SYSTICK_START = 206, 
    TRIG_SIG_AON_SYSTICK_IRQ = 207, 
    TRIG_SIG_AON_SYSTICK_EMIT = 208, 
    TRIG_SIG_WAKEUP_SRC_RDY = 209, 
    TRIG_SIG_TMR0_IRQ = 210, 
    TRIG_SIG_TMR1_IRQ = 211, 
    TRIG_SIG_TMR2_IRQ = 212, 
    TRIG_SIG_TMR3_IRQ = 213, 
    TRIG_SIG_TMR4_IRQ = 214, 
    TRIG_SIG_TMR5_IRQ = 215, 
    TRIG_SIG_AON_TMR2_EMIT0 = 216, 
    TRIG_SIG_AON_TMR2_EMIT1 = 217, 
    TRIG_SIG_AON_TMR2_CAP0 = 218, 
    TRIG_SIG_AON_TMR2_CAP1 = 219, 
    TRIG_SIG_TMR0_EMIT0 = 220, 
    TRIG_SIG_TMR0_EMIT1 = 221, 
    TRIG_SIG_TMR0_EMIT2 = 222, 
    TRIG_SIG_TMR0_EMIT3 = 223, 
    TRIG_SIG_TMR0_EMIT4 = 224, 
    TRIG_SIG_TMR0_EMIT5 = 225, 
    TRIG_SIG_TMR0_EMIT6 = 226, 
    TRIG_SIG_TMR0_EMIT7 = 227, 
    TRIG_SIG_CPLL_RST = 228, 
    TRIG_SIG_CPLL_EN = 229, 
    TRIG_SIG_CPLL_LOCKED = 230, 
    TRIG_SIG_MPLL_RST = 231, 
    TRIG_SIG_MPLL_EN = 232, 
    TRIG_SIG_MPLL_LOCKED = 233, 
    TRIG_SIG_SYSTICK = 234, 
    TRIG_SIG_SYSTICK_IRQ = 235, 
    TRIG_SIG_CPU_IRQ0 = 236, 
    TRIG_SIG_CPU_IRQ1 = 237, 
    TRIG_SIG_CPU_IRQ2 = 238, 
    TRIG_SIG_CPU_IRQ3 = 239, 
    TRIG_SIG_CPU_IRQ4 = 240, 
    TRIG_SIG_CPU_IRQ5 = 241, 
    TRIG_SIG_CPU_IRQ6 = 242, 
    TRIG_SIG_CPU_IRQ7 = 243, 
    TRIG_SIG_BLE_CLKN_MATCH0 = 244, 
    TRIG_SIG_BLE_CLKN_MATCH1 = 245, 
    TRIG_SIG_SYSTEM_BUS_HIT = 249, 
    TRIG_SIG_DATA_BUS_HIT = 250, 
    TRIG_SIG_PC_HIT = 251, 
    TRIG_SIG_SW0 = 252, 
    TRIG_SIG_SW1 = 253, 
    TRIG_SIG_SW2 = 254, 
    TRIG_SIG_DISABLE = 255, 
};

enum trig_ble_irq_t {
    TRIG_BLE_IRQ_SW = 0, 
    TRIG_BLE_IRQ_FINE = 1, 
    TRIG_BLE_IRQ_GROSS = 2, 
    TRIG_BLE_IRQ_TS = 3, 
    TRIG_BLE_IRQ_ERR = 4, 
    TRIG_BLE_IRQ_CRYPT = 5, 
    TRIG_BLE_IRQ_START = 6, 
    TRIG_BLE_IRQ_END = 7, 
    TRIG_BLE_IRQ_SKIP = 8, 
    TRIG_BLE_IRQ_SLEEP = 9, 
    TRIG_BLE_IRQ_TX = 10, 
    TRIG_BLE_IRQ_RX = 11, 
    TRIG_BLE_IRQ_HALF_SLOT = 12, 
    TRIG_BLE_IRQ_EVT_FSM_TIMEOUT = 13, 
    TRIG_BLE_IRQ_CLKN_MISS = 15, 
    TRIG_BLE_IRQ_CLKN_MATCH = 19, 
    TRIG_BLE_IRQ_EVT_TIMEOUT = 20, 
    TRIG_BLE_IRQ_FSM_TIMEOUT = 21, 
};

enum trig_timer_val_t {
    TRIG_TMR_CMD = 0, 
    TRIG_TMR_REG = 1, 
};

enum trig_reg_cp_len_t {
    TRIG_REG_1_BYTE = 0, 
    TRIG_REG_2_BYTES = 1, 
    TRIG_REG_4_BYTES = 2, 
};

enum trig_reg_bus_t {
    TRIG_REG_AHB = 0, 
    TRIG_REG_APB = 1, 
};

enum trig_reg_comp_cond_t {
    TRIG_REG_EQUAL = 0, 
    TRIG_REG_NOT_EQUAL = 1, 
    TRIG_REG_LARGER = 2, 
    TRIG_REG_LESS = 3, 
};

enum trig_apb_mux_t {
    TRIG_APB_MSPI0 = 0, 
    TRIG_APB_MSPI1 = 1, 
    TRIG_APB_SSPI = 2, 
    TRIG_APB_UART0 = 3, 
    TRIG_APB_UART1 = 4, 
    TRIG_APB_I2C0 = 5, 
    TRIG_APB_I2C1 = 6, 
    TRIG_APB_TMR = 7, 
    TRIG_APB_ADC = 8, 
    TRIG_APB_GLOBAL = 9, 
    TRIG_APB_TRIG = 10, 
    TRIG_APB_PWM = 11, 
    TRIG_APB_SHM = 12, 
    TRIG_APB_TRX_SEQ = 13, 
    TRIG_APB_TRX = 14, 
    TRIG_APB_GLOBAL2 = 15, 
    TRIG_APB_TMR_ADD = 16, 
    TRIG_APB_MAX,
};

typedef struct {
    int irq_prio; 
    int auto_resume; 
    void (*irq_cb)(void *arg, uint32_t status0, uint32_t status1);  
    void* cb_arg; 
    uint32_t intr_unmask0; 
    uint32_t intr_unmask1; 
    uint32_t mp_mem_addr; 
    uint32_t lp_mem_addr; 
} trig_init_t;

typedef struct {
    uint16_t cmd_addr; 
    uint16_t cmd_num;  
    uint8_t run_until_null; 
    uint8_t run_until_invalid; 
} trig_hdr_t;

typedef struct {
    int odc_idx[TRIG_ODC_MAX_OUTPUT_NUM]; 
    uint8_t init_value[TRIG_ODC_MAX_OUTPUT_NUM]; 
    uint8_t value[TRIG_ODC_MAX_OUTPUT_NUM]; 
    uint8_t toggle_en[TRIG_ODC_MAX_OUTPUT_NUM]; 
} trig_output_cmd_t;

typedef struct {
    int auto_reload; 
    int init_src; 
    int reload_src; 
    uint32_t init_value; 
} trig_set_tmr_cmd_t;

typedef struct {
    int stop_timer; 
    uint32_t target_time; 
} trig_wait_tmr_cmd_t;

typedef struct {
    int cont_cmp; 
    int cmp_cond; 
    int reg_bus; 
    uint32_t fail_cmd_addr; 
    uint32_t wait_time; 
    uint32_t max_rd_num; 
    uint32_t reg_addr; 
    uint32_t mask; 
    uint32_t exp_value; 
} trig_reg_rd_cmp_cmd_t;

typedef struct {
    int reg_bus; 
    uint32_t write_value; 
    uint32_t reg_addr; 
} trig_reg_wr_cmd_t;

typedef struct {
    int reg_bus; 
    uint32_t write_value; 
    uint32_t reg_addr; 
    uint32_t mask; 
} trig_reg_rw_cmd_t;

typedef struct {
    int size; 
    int src_bus; 
    int dst_bus; 
    uint32_t src_addr; 
    uint32_t dst_addr; 
} trig_reg_cp_cmd_t;

typedef struct {
    int size; 
    int src_bus; 
    int dst_bus; 
    uint32_t src_addr; 
    uint32_t dst_addr; 
    uint32_t mask; 
} trig_reg_mask_cp_cmd_t;

typedef struct {
    int sig_idx; 
    int rising_edge; 
    int falling_edge; 
} trig_sig_t;


static INLINE uint32_t trig_intr_status(void)
{
    return RD_WORD(TRIG_HANDLER_REGS_INTR_STATUS);
}
static INLINE void trig_intr_clear(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_CLEAR, val);
}
static INLINE void trig_intr_mask(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_SET, val);
}
static INLINE void trig_intr_unmask(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_CLEAR, val);
}
static INLINE uint32_t trig_intr_status1(void)
{
    return RD_WORD(TRIG_HANDLER_REGS_INTR_STATUS_1);
}
static INLINE void trig_intr_clear1(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_CLEAR_1, val);
    WR_WORD(TRIG_HANDLER_REGS_INTR_CLEAR, 0);
    WR_WORD(TRIG_HANDLER_REGS_INTR_CLEAR_1, 0);
}
static INLINE void trig_intr_mask1(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_SET_1, val);
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_SET, 0);
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_SET_1, 0);
}
static INLINE void trig_intr_unmask1(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_CLEAR_1, val);
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_CLEAR, 0);
    WR_WORD(TRIG_HANDLER_REGS_INTR_MASK_CLEAR_1, 0);
}


static INLINE void trig_en(int en)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MISC_CTRL);
    if (en) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_TRIG_HANDLER_EN;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_TRIG_HANDLER_EN;
    }
    WR_WORD(TRIG_HANDLER_REGS_MISC_CTRL, reg);
}
static INLINE void trig_hp_queue_en(int en, int invalid_cmd)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MISC_CTRL);
    if (en) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_HP_QUEUE_EN;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_HP_QUEUE_EN;
    }
    if (invalid_cmd) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_HP_INVALID_CMD_CONT;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_HP_INVALID_CMD_CONT;
    }
    WR_WORD(TRIG_HANDLER_REGS_MISC_CTRL, reg);  
}
static INLINE void trig_mp_queue_en(int en, int invalid_cmd)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MISC_CTRL);
    if (en) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_MP_QUEUE_EN;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_MP_QUEUE_EN;
    }
    if (invalid_cmd) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_MP_INVALID_CMD_CONT;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_MP_INVALID_CMD_CONT;
    }
    WR_WORD(TRIG_HANDLER_REGS_MISC_CTRL, reg);  
}
static INLINE void trig_lp_queue_en(int en, int invalid_cmd)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MISC_CTRL);
    if (en) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_LP_QUEUE_EN;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_LP_QUEUE_EN;
    }
    if (invalid_cmd) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_LP_INVALID_CMD_CONT;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_LP_INVALID_CMD_CONT;
    }
    WR_WORD(TRIG_HANDLER_REGS_MISC_CTRL, reg);  
}
static INLINE void trig_dedmem_sw_access_en(int en)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MISC_CTRL);
    if (en) {
        reg |= TRIG_HANDLER_REGS_MISC_CTRL_CTL_DEDM_SW_ACCESS_EN;
    } else {
        reg &=~TRIG_HANDLER_REGS_MISC_CTRL_CTL_DEDM_SW_ACCESS_EN;
    }
    WR_WORD(TRIG_HANDLER_REGS_MISC_CTRL, reg);
}
static INLINE void trig_dedmem_wr_init_addr(uint32_t addr)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_DEDM_INI_ADDR);
    reg &= ~TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_WR_INI_ADDR;
    reg |= (addr&TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_WR_INI_ADDR_MASK)<<TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_WR_INI_ADDR_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_DEDM_INI_ADDR, addr);
}
static INLINE void trig_dedmem_rd_init_addr(uint32_t addr)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_DEDM_INI_ADDR);
    reg &= ~TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_RD_INI_ADDR;
    reg |= (addr&TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_RD_INI_ADDR_MASK)<<TRIG_HANDLER_REGS_DEDM_INI_ADDR_CTL_DEDM_RD_INI_ADDR_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_DEDM_INI_ADDR, addr);
}
static INLINE void trig_dedmem_wr_data(uint32_t data)
{
    WR_WORD(TRIG_HANDLER_REGS_DEDM_WDATA, data);
}
static INLINE uint32_t trig_dedmem_rd_data(void)
{
    return RD_WORD(TRIG_HANDLER_REGS_DEDM_RDATA);
}
static INLINE void  trig_sw_trig(int en, uint32_t sw_id)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_SW_TRIG);
    if (en) {
        reg |= 1<<sw_id;
    } else {
        reg &= ~(1<<sw_id);
    }
    WR_WORD(TRIG_HANDLER_REGS_SW_TRIG, reg);
}
static INLINE void trig_set_lp_mem_addr(uint32_t addr_offset)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET);
    reg &= ~TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_LP_MEM_ADDR_OFFSET;
    reg |= (addr_offset & TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_LP_MEM_ADDR_OFFSET_MASK)<<TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_LP_MEM_ADDR_OFFSET_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET, reg);
}
static INLINE void trig_set_mp_mem_addr(uint32_t addr_offset)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET);
    reg &= ~TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_MP_MEM_ADDR_OFFSET;
    reg |= (addr_offset & TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_MP_MEM_ADDR_OFFSET_MASK)<<TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_MP_MEM_ADDR_OFFSET_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET, reg);
}
static INLINE uint32_t trig_get_lp_mem_addr(void)
{
    return (RD_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET)>>TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_LP_MEM_ADDR_OFFSET_SHIFT)&TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_LP_MEM_ADDR_OFFSET_MASK;
}
static INLINE uint32_t trig_get_mp_mem_addr(void)
{
    return (RD_WORD(TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET)>>TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_MP_MEM_ADDR_OFFSET_SHIFT)&TRIG_HANDLER_REGS_MP_LP_MEM_ADDR_OFFSET_CTL_MP_MEM_ADDR_OFFSET_MASK;
}
static INLINE void trig_hp_trig_idx(uint8_t trig_id, uint8_t sig_idx)
{
    uint32_t addr, reg, shift;
    if (trig_id/4)
        addr = TRIG_HANDLER_REGS_HP_TRIG_IDX_GROUP_1;
    else
        addr = TRIG_HANDLER_REGS_HP_TRIG_IDX_GROUP_0;
    shift = (trig_id%4)*8;
    reg = RD_WORD(addr);
    reg &= ~(0xFF<<shift);
    reg |= sig_idx<<shift;
    WR_WORD(addr, reg);
}
static INLINE void trig_mp_trig_idx(uint8_t trig_id, uint8_t sig_idx)
{
    uint32_t addr, reg, shift;
    if (trig_id/4)
        addr = TRIG_HANDLER_REGS_MP_TRIG_IDX_GROUP_1;
    else
        addr = TRIG_HANDLER_REGS_MP_TRIG_IDX_GROUP_0;
    shift = (trig_id%4)*8;
    reg = RD_WORD(addr);
    reg &= ~(0xFF<<shift);
    reg |= sig_idx<<shift;
    WR_WORD(addr, reg);
}
static INLINE void trig_lp_trig_idx(uint8_t trig_id, uint8_t sig_idx)
{
    uint32_t addr, reg, shift;
    uint8_t group = trig_id/4;
    if (group == 1)
        addr = TRIG_HANDLER_REGS_LP_TRIG_IDX_GROUP_1;
    else if (group == 2)
        addr = TRIG_HANDLER_REGS_LP_TRIG_IDX_GROUP_2;
    else if (group == 3)
        addr = TRIG_HANDLER_REGS_LP_TRIG_IDX_GROUP_3;
    else
        addr = TRIG_HANDLER_REGS_LP_TRIG_IDX_GROUP_0;
    shift = (trig_id%4)*8;
    reg = RD_WORD(addr);
    reg &= ~(0xFF<<shift);
    reg |= sig_idx<<shift;
    WR_WORD(addr, reg);
}
static INLINE void trig_hp_rising_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_SET_CTL_HP_TRIG_RISE_EDGE_EN_SET_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_SET_CTL_HP_TRIG_RISE_EDGE_EN_SET_SHIFT));
    }
}
static INLINE void trig_mp_rising_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR_CTL_MP_TRIG_RISE_EDGE_EN_CLR_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR_CTL_MP_TRIG_RISE_EDGE_EN_CLR_SHIFT));
    }
}
static INLINE void trig_lp_rising_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR_CTL_LP_TRIG_RISE_EDGE_EN_CLR_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_RISE_EDGE_EN_CLR_CTL_LP_TRIG_RISE_EDGE_EN_CLR_SHIFT));
    }
}
static INLINE void trig_hp_falling_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_HP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_HP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    }
}
static INLINE void trig_mp_falling_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_MP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_MP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    }
}
static INLINE void trig_lp_falling_edge_en(uint8_t trig_id, int en)
{
    if (en) {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_LP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    } else {
        WR_WORD(TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET, 1<<(trig_id+TRIG_HANDLER_REGS_TRIG_FALL_EDGE_EN_SET_CTL_LP_TRIG_FALL_EDGE_EN_SET_SHIFT));
    }
}

static INLINE void trig_ctl_gpio_out_0(int en, uint32_t idx)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OUT_0);
    if (en) {
        reg |= 1<<idx;
    } else {
        reg &= ~(1<<idx);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OUT_0, reg);
}
static INLINE void trig_ctl_gpio_out_1(int en, uint32_t idx)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OUT_1);
    if (en) {
        reg |= 1<<idx;
    } else {
        reg &= ~(1<<idx);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OUT_1, reg);
}
static INLINE void trig_ctl_gpio_oe_0(int en, uint32_t idx)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OE_0);
    if (en) {
        reg |= 1<<idx;
    } else {
        reg &= ~(1<<idx);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OE_0, reg);
}
static INLINE void trig_ctl_gpio_oe_1(int en, uint32_t idx)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OE_1);
    if (en) {
        reg |= 1<<idx;
    } else {
        reg &= ~(1<<idx);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_CTL_GPIO_OE_1, reg);
}


static INLINE void trig_hdl_apb_mux(uint32_t pos, uint32_t val)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_APB_MASTER_MUX_CTRL);
    if (val) {
        reg |= 1<<pos;
    } else {
        reg &= ~(1<<pos);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_APB_MASTER_MUX_CTRL, reg);
}

static INLINE void trig_hp_tmr_init_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_HP_INI_TIMER_VALUE, val);
}

static INLINE void trig_mp_tmr_init_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_MP_INI_TIMER_VALUE, val);
}

static INLINE void trig_lp_tmr_init_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_LP_INI_TIMER_VALUE, val);
}

static INLINE void trig_hp_tmr_reload_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_HP_RELOAD_TIMER_VALUE, val);
}

static INLINE void trig_mp_tmr_reload_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_MP_RELOAD_TIMER_VALUE, val);
}

static INLINE void trig_lp_tmr_reload_tick(uint32_t val)
{
    WR_WORD(TRIG_HANDLER_REGS_LP_RELOAD_TIMER_VALUE, val);
}

static INLINE void trig_apb_mux(uint32_t pos, int apb_sel)
{
    uint32_t reg = RD_WORD(GLOBAL2_REG_TRIG_HANDLR_APB_MASTER_MUX_CTRL);
    if (apb_sel) {
        reg |= 1<<pos;
    } else {
        reg &= ~(1<<pos);
    }
    WR_WORD(GLOBAL2_REG_TRIG_HANDLR_APB_MASTER_MUX_CTRL, reg);
}

static INLINE void trig_odc_init_val(uint32_t sig0, uint32_t val0, uint32_t sig1, uint32_t val1)
{
    uint32_t reg;
    reg  = ((sig0&TRIG_HANDLER_REGS_ODC_INI_VAL_CTL_ODC_IDX_0_MASK)<<TRIG_HANDLER_REGS_ODC_INI_VAL_CTL_ODC_IDX_0_SHIFT) 
            | ((val0&0x1)<<15) 
            | ((sig1&TRIG_HANDLER_REGS_ODC_INI_VAL_CTL_ODC_IDX_1_MASK)<<TRIG_HANDLER_REGS_ODC_INI_VAL_CTL_ODC_IDX_1_SHIFT) 
            | ((val1&0x1)<<31);
    WR_WORD(TRIG_HANDLER_REGS_ODC_INI_VAL, reg);
}

static INLINE void trig_hp_intr_sig(uint8_t sig)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX);
    reg &= ~TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_HP_SPECIFIED_TRIG_IDX;
    reg |= (sig&TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_HP_SPECIFIED_TRIG_IDX_MASK)<<TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_HP_SPECIFIED_TRIG_IDX_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX, reg);
}
static INLINE void trig_mp_intr_sig(uint8_t sig)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX);
    reg &= ~TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_MP_SPECIFIED_TRIG_IDX;
    reg |= (sig&TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_MP_SPECIFIED_TRIG_IDX_MASK)<<TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_MP_SPECIFIED_TRIG_IDX_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX, reg);
}
static INLINE void trig_lp_intr_sig(uint8_t sig)
{
    uint32_t reg = RD_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX);
    reg &= ~TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_LP_SPECIFIED_TRIG_IDX;
    reg |= (sig&TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_LP_SPECIFIED_TRIG_IDX_MASK)<<TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX_CTL_LP_SPECIFIED_TRIG_IDX_SHIFT;
    WR_WORD(TRIG_HANDLER_REGS_SPECIFIED_TRIG_IDX, reg);
}
int hal_trig_open(trig_init_t *init);

void hal_trig_close(void);

int hal_trig_set_mem_addr(int queue, uint32_t mem_addr);

int hal_trig_queue_enable(int queue);

int hal_trig_queue_disable(int queue);

int hal_trig_wr_header(int queue, int trig_id, trig_hdr_t *hdr);

int hal_trig_output_cmd(int queue, uint32_t addr_offset, trig_output_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_set_tmr_cmd(int queue, uint32_t addr_offset, trig_set_tmr_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_wait_tmr_cmd(int queue, uint32_t addr_offset, trig_wait_tmr_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_reg_rd_cmp_cmd(int queue, uint32_t addr_offset, trig_reg_rd_cmp_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_reg_wr_cmd(int queue, uint32_t addr_offset, trig_reg_wr_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_reg_rw_cmd(int queue, uint32_t addr_offset, trig_reg_rw_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_reg_copy_cmd(int queue, uint32_t addr_offset, trig_reg_cp_cmd_t* cmd, uint32_t *cmd_addr_oft);

int hal_trig_reg_mask_copy_cmd(int queue, uint32_t addr_offset, trig_reg_mask_cp_cmd_t* cmd, uint32_t *cmd_addr_oft);


int hal_trig_set_sig(int queue, int trig_id, trig_sig_t* sig);

int hal_trig_odc_gpio_output_en(int port, int pin, int en);

int hal_trig_odc_gpio_oen_en(int port, int pin, int en);
int hal_trig_odc_gpio_output_idx(int port, int pin);

int hal_trig_odc_gpio_oen_idx(int port, int pin);
int hal_trig_sig_gpio_input_idx(int port, int pin);

int hal_trig_sig_gpio_ie_oe_idx(int port, int pin);

int hal_trig_sig_gpio_output_idx(int port, int pin);

int hal_trig_null_cmd(int queue, uint32_t addr_offset, uint32_t *cmd_addr_oft);

uint32_t hal_trig_curr_cmd_addr(int queue);

int hal_trig_sig_gpio_ie_oe(int port, int pin, int oe);

int hal_trig_sig_ble_irq(int idx, uint8_t irq_signal);

int hal_trig_sig_cpu_irq(int idx, uint8_t irq_num);

int hal_trig_tmr_init_tick(int queue, uint32_t init_val);
int hal_trig_tmr_reload_tick(int queue, uint32_t reload_val);

int hal_trig_apb_mux(int peripheral, int bus_sel);

void hal_trig_resume(void);

int hal_trig_intr_sig(int queue, int trig_sig);

#endif