InPlay API
hal_clk.h
1 
13 #ifndef HAL_CLK_H
14 #define HAL_CLK_H
15 
25 #include "in_mmap.h"
26 #include "in_compile.h"
27 
28 /*
29  * Enumerations
30  ****************************************************************************************
31  */
32 
34 enum clk_d0_div {
36  CLK_D0_DIV1 = 1,
38  CLK_D0_DIV2= 0,
39  };
40 
42 enum clk_d1_div {
44  CLK_D1_DIV2 = 1,
46  CLK_D1_DIV4 = 2,
48  CLK_D1_DIV8 = 3,
49 };
50 
52 enum clk_d2_div {
54  CLK_D2_DIV1 = 0,
56  CLK_D2_DIV2 = 1,
58  CLK_D2_DIV4 = 3,
59 };
60 
62 enum clk_tim_div {
64  CLK_TIM_DIV4 = 1,
66  CLK_TIM_DIV8 = 2,
68  CLK_TIM_DIV2 = 3,
69 };
70 
72 enum clk_sdm_mux {
74  CLK_I2S_MSTR_SCLK,
76  CLK_I2S_SLV_SCLK_PAD,
78  CLK_PDM,
79 };
80 
82 enum clk_efuse_div {
84  CLK_EFUSE_DIV4 = 0,
86  CLK_EFUSE_DIV8,
87 };
88 
90 enum clk_smem_div {
92  CLK_SMEM_DIV1 = 0,
94  CLK_SMEM_DIV2 = 1,
96  CLK_SMEM_DIV4 = 3,
98  CLK_SMEM_DIV8 = 7,
99 };
100 
102 enum clk_qspi_div {
104  CLK_QSPI_DIV1 = 0,
106  CLK_QSPI_DIV2 = 1,
108  CLK_QSPI_DIV4 = 3,
110  CLK_QSPI_DIV8 = 7,
111 };
112 
114 enum clk_systick_div {
116  CLK_SYSTICK_DIV4 = 1,
118  CLK_SYSTICK_DIV8 = 2,
120  CLK_SYSTICK_DIV16 = 3,
121 };
122 
123 
125 enum clk_error {
127  CLK_ERR_NO_ERROR = 0,
129  CLK_ERR_INVALID_PARAM = -1,
130 };
131 
132 /*
133  * Inline Functions
134  ****************************************************************************************
135  */
136 #if defined (__CC_ARM)
137 #pragma push
138 #pragma O0
139 #elif defined (__GNUC__) /* GNU Compiler */
140 #pragma GCC push_options
141 #pragma GCC optimize ("O0")
142 #endif
143 static INLINE void clk_delay(uint32_t us)
144 {
145  uint32_t reg = RD_WORD(D2_REG_CLK_CTRL);
146  if (!(reg & D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XOX2_OR_XO)) { // 64
147  us *= 2;
148  }
149  reg = (RD_WORD(GLOBAL_REG_CLK_CTRL_1) >> GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_SHIFT) & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_MASK;
150 
151  if (reg & 2)
152  us >>= 2;
153  else if (reg & 1)
154  us >>= 1;
155  us >>= 1;//Need div 2 here
156  if (us == 0)
157  us = 1;
158 
159  for (uint32_t k = 0; k < (us * 6); k++)
160  __nop() ;
161 }
162 #if defined (__CC_ARM)
163 #pragma pop
164 #elif defined (__GNUC__)
165 #pragma GCC pop_options
166 #endif
167 static INLINE void clk_xo_ps_opt(uint32_t stable_time)
168 {
169  WR_WORD(AON_PS_REGS_DCDC_EN_DELAY_CTRL, 0x4);
170  WR_WORD(AON_PS_REGS_ON_DELAY_0_CTRL, stable_time);
171  WR_WORD(AON_PS_REGS_ON_DELAY_1_CTRL, 0x14020018);
172  WR_WORD(AON_PS_REGS_XO_EN_DELAY_CTRL, 0x402);
173  WR_WORD(AON_PS_REGS_OFF_DELAY_0_CTRL, 0x2010000);
174  WR_WORD(AON_PS_REGS_OFF_DELAY_1_CTRL, 0x3040002);
175 }
176 
177 static INLINE void clk_xo_stage_delay(uint32_t stage0_delay, uint32_t stage1_delay)
178 {
179  uint32_t reg = RD_WORD(AON_REG_XO_EN_STAGE_CTRL);
180  reg &= ~(AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE0_DURATION|AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE1_DURATION);
181  reg |= (stage0_delay & AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE0_DURATION_MASK) << AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE0_DURATION_SHIFT;
182  reg |= (stage1_delay & AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE1_DURATION_MASK) << AON_REG_XO_EN_STAGE_CTRL_CTL_XO_STAGE1_DURATION_SHIFT;
183  WR_WORD(AON_REG_XO_EN_STAGE_CTRL, reg);
184 }
185 
186 static INLINE void clk_xo_delay(uint32_t cycles)
187 {
188  WR_WORD(AON_PS_REGS_ON_DELAY_0_CTRL, (cycles & AON_PS_REGS_ON_DELAY_0_CTRL_CLOCK_EN_EARLY_PD_DOO_MASK));
189 }
190 
191 static INLINE void clk_xo_cap(uint32_t cap)
192 {
193  uint32_t reg = RD_WORD(AON_REG_XO_STAGE_1_REG);
194  reg &= ~0xFF;
195  reg |= (cap & 0xF) | ((cap & 0xF) << 4);
196  WR_WORD(AON_REG_XO_STAGE_1_REG, reg);
197 }
198 
199 static INLINE void clk_xo_gm(uint32_t gm)
200 {
201  uint32_t reg = RD_WORD(AON_REG_XO_STAGE_1_REG);
202  reg &= ~(0x1F << 8);
203  reg |= (gm & 0x1F) << 8;
204  WR_WORD(AON_REG_XO_STAGE_1_REG, reg);
205 }
206 
207 static INLINE void clk_xo_x2(int en)
208 {
209  //uint32_t reg = RD_WORD(AON_REG_XO_REG);
210  uint32_t reg2 = RD_WORD(AON_REG_XO_STAGE_1_REG);
211  if (en) {
212  //reg |= (1 << 15);
213  reg2 |= (1 << 15);
214  } else {
215  //reg &= ~(1 << 15);
216  reg2 &= ~(1 << 15);
217  }
218  //WR_WORD(AON_REG_XO_REG, reg);
219  WR_WORD(AON_REG_XO_STAGE_1_REG, reg2);
220 }
221 
222 static INLINE void clk_xo_2x_current(int en)
223 {
224  uint32_t reg = RD_WORD(AON_REG_XO_STAGE_1_REG);
225  if (en) {
226  reg |= (1 << 16);
227  } else {
228  reg &= ~(1 << 16);
229  }
230  WR_WORD(AON_REG_XO_STAGE_1_REG, reg);
231 }
232 
233 static INLINE void clk_xo_amp(uint32_t target)
234 {
235  uint32_t reg = RD_WORD(AON_REG_XO_STAGE_1_REG);
236  reg &= ~(0x7 << 19);
237  reg |= (target & 0x7) << 19;
238  WR_WORD(AON_REG_XO_STAGE_1_REG, reg);
239 }
240 
241 static INLINE void clk_xo_peak_det(int en)
242 {
243  uint32_t reg = RD_WORD(AON_REG_XO_STAGE_1_REG);
244  if (en) {
245  reg |= (1 << 24);
246  } else {
247  reg &= ~(1 << 24);
248  }
249  WR_WORD(AON_REG_XO_STAGE_1_REG, reg);
250 }
251 
252 static INLINE uint32_t clk_xo_status(void)
253 {
254  return (RD_WORD(RFTRX_REG_XO_STATUS));
255 }
256 
257 static INLINE void clk_root_rc_32mhz(void)
258 {
259 
260  uint32_t clk_enable_2, rc_clk_sel, rftrx;
262  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
263 
264  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN;
265  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
266  RD_WORD(GLOBAL_REG_CLK_ENABLE_2); //Read back to add some delay here
267 
268 
270  rc_clk_sel = RD_WORD(D2_REG_RC_CLOCK_SEL);
271 
272  rc_clk_sel &= ~D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC;
273  WR_WORD(D2_REG_RC_CLOCK_SEL, rc_clk_sel);
274  RD_WORD(D2_REG_RC_CLOCK_SEL);
275 
277  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN|
278  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN|
279  GLOBAL_REG_CLK_ENABLE_2_CTL_TRX_CPLL_TO_DIGI_EN|
280  GLOBAL_REG_CLK_ENABLE_2_CTL_TRX_CPLL_TO_DIGI_DIV2_EN);
281  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
282 
283  rftrx=RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
284 
285  rftrx &=~(RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN|RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN);
286  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL,rftrx);
287 
288 
289 }
290 
291 static INLINE void clk_root_xo_64mhz(void)
292 {
293  uint32_t rftrx_misc_ctrl, clk_enable_2, clk_ctrl, rc_clk_sel;
294 
296  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
297  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN;
298  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
299 
301  rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
302  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN;
303  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
304  RD_WORD(GLOBAL_REG_CLK_ENABLE_2);//Read back to add some delay here
305  //clk_delay(10);
306 
308  clk_ctrl = RD_WORD(D2_REG_CLK_CTRL);
309  clk_ctrl &= ~D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XOX2_OR_XO;
310  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
311 
313  rc_clk_sel = RD_WORD(D2_REG_RC_CLOCK_SEL);
314  rc_clk_sel |= D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC;
315  WR_WORD(D2_REG_RC_CLOCK_SEL, rc_clk_sel);
316 
318  clk_ctrl &= ~D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
319  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
320 
322  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN|
323  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN|
324  GLOBAL_REG_CLK_ENABLE_2_CTL_TRX_CPLL_TO_DIGI_EN|
325  GLOBAL_REG_CLK_ENABLE_2_CTL_TRX_CPLL_TO_DIGI_DIV2_EN);
326  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
327 
329  rftrx_misc_ctrl &= ~RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN;
330  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
331 
332 }
333 
334 static INLINE void clk_root_xo_32mhz(int cold)
335 {
336  uint32_t rftrx_misc_ctrl, clk_enable_2, clk_ctrl, rc_clk_sel ;
337 
339  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
340  if (cold) {
341  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN;
342  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
343  }
344 
346  rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
347  if (cold) {
348  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN;
349  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
350  RD_WORD(GLOBAL_REG_CLK_ENABLE_2);//Read back to add some delay here
351  }
352  //clk_delay(10);
353  // select 32M root clock
354  if (cold) {
355  clk_ctrl = RD_WORD(D2_REG_CLK_CTRL);
356  clk_ctrl |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XOX2_OR_XO;
357  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
358  }
359 
361  rc_clk_sel = RD_WORD(D2_REG_RC_CLOCK_SEL);
362  rc_clk_sel |= D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC;
363  WR_WORD(D2_REG_RC_CLOCK_SEL, rc_clk_sel);
364 
366  if (cold) {
367  clk_ctrl &= ~D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
368  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
369  }
370 
371  // Disable XO_X2 & RC
372  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN|
373  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN);
374  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
375 
377  rftrx_misc_ctrl &= ~RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN;
378  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
379 
380 }
381 
382 static INLINE void clk_root_cpll_32mhz(void)
383 {
385  uint32_t rftrx_misc_ctrl, clk_enable_2, clk_ctrl, cpll_ctrl;
386 
388  rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
389  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_CPLL_TO_DIGI_EN;
390  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
391 
393  cpll_ctrl = RD_WORD(AON_REG_CPLL_CTRL);
394  cpll_ctrl &= ~AON_REG_CPLL_CTRL_CTL_CPLL_FREQ_SEL; // 64 Mhz
395  cpll_ctrl |= AON_REG_CPLL_CTRL_CTL_CPLL_EN|AON_REG_CPLL_CTRL_CTL_BGR_EN;
396  WR_WORD(AON_REG_CPLL_CTRL, cpll_ctrl);
397 
399  while (!(RD_WORD(GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS) & GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS_STS_CPLL_CTRL_CPLL_LOCKED));
400 
401  // clk_enable_2
402  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
403  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_DIV2_CLK_EN; // CPLL/2
404  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_CLK_EN;
405  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
406 
407  // clk_ctrl
408  clk_ctrl = D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_CPLL_OR_CPLL_DIV2;
409  clk_ctrl |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
410  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
411  WR_WORD(D2_REG_RC_CLOCK_SEL, D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC);
412 
413  // Disable XO, XO_X2
414  rftrx_misc_ctrl &= ~(RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN|RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN);
415  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
416 
417  // Disable XO, XO_X2 & RC
418  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN|
419  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN|
420  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN);
421  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
422 
423 }
424 
425 static INLINE void clk_root_cpll_64mhz(void)
426 {
428  uint32_t rftrx_misc_ctrl, clk_enable_2, clk_ctrl, cpll_ctrl;
429 
431  rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
432  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_CPLL_TO_DIGI_EN;
433  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
434 
436  cpll_ctrl = RD_WORD(AON_REG_CPLL_CTRL);
437  cpll_ctrl &= ~AON_REG_CPLL_CTRL_CTL_CPLL_FREQ_SEL;
438  cpll_ctrl |= AON_REG_CPLL_CTRL_CTL_CPLL_EN|AON_REG_CPLL_CTRL_CTL_BGR_EN;
439  WR_WORD(AON_REG_CPLL_CTRL, cpll_ctrl);
440 
442  while (!(RD_WORD(GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS) & GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS_STS_CPLL_CTRL_CPLL_LOCKED));
443 
444  // clk_enable_2
445  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
446  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_DIV2_CLK_EN; // CPLL/2
447  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_CLK_EN;
448  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
449 
450  // clk_ctrl
451  clk_ctrl |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
452  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
453  WR_WORD(D2_REG_RC_CLOCK_SEL, D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC);
454 
455  // Disable XO, XO_X2
456  rftrx_misc_ctrl &= ~(RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN|RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN);
457  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
458 
459  // Disable XO, XO_X2 & RC
460  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN|
461  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN|
462  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN);
463  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
464 
465 }
466 
467 static INLINE void clk_root_cpll_128mhz(void)
468 {
470  uint32_t rftrx_misc_ctrl, clk_enable_2, clk_ctrl, cpll_ctrl;
471 
473  rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
474  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_CPLL_TO_DIGI_EN;
475  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
476 
478  cpll_ctrl = RD_WORD(AON_REG_CPLL_CTRL);
479  cpll_ctrl |= AON_REG_CPLL_CTRL_CTL_CPLL_EN|AON_REG_CPLL_CTRL_CTL_BGR_EN|AON_REG_CPLL_CTRL_CTL_CPLL_FREQ_SEL;
480  WR_WORD(AON_REG_CPLL_CTRL, cpll_ctrl);
481 
483  while (!(RD_WORD(GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS) & GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS_STS_CPLL_CTRL_CPLL_LOCKED));
484 
485  // clk_enable_2
486  clk_enable_2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
487  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_CLK_EN; // CPLL
488  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_DIV2_CLK_EN;
489  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
490 
491  // clk_ctrl
492  clk_ctrl = D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_CPLL_OR_CPLL_DIV2;
493  clk_ctrl |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
494  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
495  WR_WORD(D2_REG_RC_CLOCK_SEL, D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC);
496 
497  // Disable XO, XO_X2
498  rftrx_misc_ctrl &= ~(RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_X2_TO_DIGI_EN|RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN);
499  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
500 
501  // Disable XO, XO_X2 & RC
502  clk_enable_2 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN|
503  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_64MXO_EN|
504  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN);
505  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
506 
507 }
508 
509 static INLINE void clk_root_cpll_resume(int freq_64mhz)
510 {
511  uint32_t clk_enable_2, clk_ctrl /*, cpll_ctrl, rc_clk_sel*/;
512 
514  clk_root_rc_32mhz();
515 
517  while (!(RD_WORD(GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS) & GLOBAL_REG_CPLL_CTRL_XO_DETECT_STATUS_STS_CPLL_CTRL_CPLL_LOCKED));
518 
520  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_ANA_CLK_32M_RC_EN;
521  if (freq_64mhz) {
522  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_CLK_EN;
523  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_DIV2_CLK_EN;
524  } else {
525  clk_enable_2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_DIV2_CLK_EN;
526  clk_enable_2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_CPLL_CLK_EN;
527  }
528  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, clk_enable_2);
529 
530  // clk_ctrl
531  if (!freq_64mhz) {
532  clk_ctrl = D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_CPLL_OR_CPLL_DIV2;
533  }
534  clk_ctrl |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL;
535  WR_WORD(D2_REG_CLK_CTRL, clk_ctrl);
536  WR_WORD(D2_REG_RC_CLOCK_SEL, D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC);
537 }
538 
539 static INLINE void clk_xo_to_digi_en(int en)
540 {
541  uint32_t reg_EN2 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
542 
543  if (en) {
544  reg_EN2 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN;
545  } else {
546  reg_EN2 &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN;
547  }
548  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, reg_EN2);
549 
550  // rftrx_misc_ctrl
551  uint32_t rftrx_misc_ctrl = RD_WORD(RFTRX_REG_RFTRX_MISC_CTRL);
552  if (en) {
553  rftrx_misc_ctrl |= RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN; // XO
554  } else {
555  rftrx_misc_ctrl &= ~RFTRX_REG_RFTRX_MISC_CTRL_CTL_CLK_XO_TO_DIGI_EN;
556  }
557  WR_WORD(RFTRX_REG_RFTRX_MISC_CTRL, rftrx_misc_ctrl);
558 }
559 
560 static INLINE void clk_xo_on(int xo_32, uint8_t capacitor, uint8_t drive_strength)
561 {
563  clk_root_rc_32mhz();
564 
566  uint32_t reg_xo = RD_WORD(AON_REG_XO_STAGE_1_REG);
567  reg_xo &= ~0x11FFF;
568  reg_xo |= capacitor | (capacitor << 4) | (drive_strength << 8);
569  WR_WORD(AON_REG_XO_STAGE_1_REG, reg_xo);
570 
572 #if 0
573  reg_xo = RD_WORD(AON_REG_XO_STAGE_1_REG);
574  reg_xo &= ~(1 << 16);
575  WR_WORD(AON_REG_XO_STAGE_1_REG, reg_xo);
576 #endif
577 
578  clk_delay(200);
579 
581  if (xo_32) {
582  clk_root_xo_32mhz(1); // XO 32Mhz
583  } else {
584  clk_root_xo_64mhz(); // XO 64Mhz
585  }
586 }
587 
588 static INLINE void clk_rc_bypass(int bypass)
589 {
590  uint32_t reg = RD_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL);
591  if (bypass) {
592  reg |= AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_EN;
593  reg &= ~AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_VAL;
594  } else {
595  reg &= ~AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_EN;
596  reg |= AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_VAL;
597  }
598  WR_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL, reg);
599 }
600 
601 static INLINE void clk_rc_bypass_en(void)
602 {
603  uint32_t reg = RD_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL);
604  reg |= AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_EN;
605  reg &= ~AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_VAL;
606  WR_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL, reg);
607 }
608 
609 static INLINE void clk_rc_bypass_dis(void)
610 {
611  uint32_t reg = RD_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL);
612  reg &= ~AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_EN;
613  reg |= AON_PS_REGS_MISC_BYPASS_0_CTRL_CLK_32MHZ_RC_EN_VAL;
614  WR_WORD(AON_PS_REGS_MISC_BYPASS_0_CTRL, reg);
615 }
616 
617 static INLINE void clk_gated_hclk_en(void)
618 {
619  WR_WORD(GLOBAL_REG_CLK_CTRL_2, (RD_WORD(GLOBAL_REG_CLK_CTRL_2)|GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_ALLOW_CM4_TO_GATE_HCLK));
620 }
621 
622 static INLINE void clk_gated_hclk_dis(void)
623 {
624  WR_WORD(GLOBAL_REG_CLK_CTRL_2, (RD_WORD(GLOBAL_REG_CLK_CTRL_2)&~GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_ALLOW_CM4_TO_GATE_HCLK));
625 }
626 
627 static INLINE void clk_mux_set(int d0_mux, int d1_mux, int d2_mux)
628 {
629  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
630 
631  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK;
632  reg |= ((d2_mux & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_SHIFT);
633  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS;
634  reg |= ((d1_mux & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS_SHIFT);
635  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
636 
637  reg = RD_WORD(D2_REG_CLK_CTRL);
638  if (d0_mux)
639  reg |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_D0_CLK;
640  else
641  reg &= ~D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_D0_CLK;
642  WR_WORD(D2_REG_CLK_CTRL, reg);
643 }
644 
645 static INLINE int clk_root_get(void)
646 {
647  int is_64 = 0;
648  uint32_t reg = RD_WORD(D2_REG_RC_CLOCK_SEL);
649 
650  if (reg & D2_REG_RC_CLOCK_SEL_CTL_CLK_CTRL_D2REG_SEL_XOCPLL_OR_32MRC) {
651  reg = RD_WORD(D2_REG_CLK_CTRL);
652  if (reg & D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XO_OR_CPLL) {
654  uint32_t reg1 = RD_WORD(AON_REG_CPLL_CTRL);
655  if (reg & D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_CPLL_OR_CPLL_DIV2) {
656  if (reg1& AON_REG_CPLL_CTRL_CTL_CPLL_FREQ_SEL) {
657  is_64 = 1;
658  }
659  } else {
660  if (reg1 & AON_REG_CPLL_CTRL_CTL_CPLL_FREQ_SEL) {
661  is_64 = 0;
662  } else {
663  is_64 = 1;
664  }
665  }
666  } else {
668  if (!(reg & D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_XOX2_OR_XO)) {
669  is_64 = 1;
670  }
671  }
672  }
673 
674  if (is_64)
675  return 64000000;
676 
677  return 32000000;
678 }
679 
680 static INLINE void clk_d0_mux(uint32_t mux)
681 {
682  uint32_t reg = RD_WORD(D2_REG_CLK_CTRL);
683 
684  if (mux)
685  reg |= D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_D0_CLK;
686  else
687  reg &= ~D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_D0_CLK;
688 
689  WR_WORD(D2_REG_CLK_CTRL, reg);
690 }
691 
692 static INLINE uint32_t clk_d0_mux_get(void)
693 {
694  uint32_t reg = RD_WORD(D2_REG_CLK_CTRL);
695 
696  if (reg & D2_REG_CLK_CTRL_CTL_CLK_CTRL_D2REG_SEL_D0_CLK)
697  return 1;
698 
699  return 0;
700 }
701 
702 static INLINE void clk_d1_mux(uint32_t clk_div)
703 {
704  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
705 
706  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS;
707  reg |= ((clk_div & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS_SHIFT);
708 
709  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
710 }
711 
712 static INLINE uint32_t clk_d1_mux_get(void)
713 {
714  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
715 
716  return ((reg & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS) >> GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D1_DIV2_4_8_CLKS_SHIFT);
717 }
718 
719 static INLINE void clk_d2_mux(uint32_t clk_div)
720 {
721  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
722 
723  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK;
724  reg |= ((clk_div & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_SHIFT);
725 
726  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
727 }
728 
729 static INLINE uint32_t clk_d2_mux_get(void)
730 {
731  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
732 
733  return ((reg & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK) >> GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D2_CLK_SHIFT);
734 }
735 
736 static INLINE uint32_t clk_d0_enable_1_get(void)
737 {
738  return (RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1));
739 }
740 
741 static INLINE void clk_d0_enable_1_set(uint32_t val)
742 {
743  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, val);
744 }
745 
746 static INLINE uint32_t clk_d0_enable_2_get(void)
747 {
748  return (RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2));
749 }
750 
751 static INLINE void clk_d0_enable_2_set(uint32_t val)
752 {
753  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, val);
754 }
755 
756 static INLINE uint32_t clk_enable_1_get(void)
757 {
758  return (RD_WORD(GLOBAL_REG_CLK_ENABLE_1));
759 }
760 
761 static INLINE void clk_enable_1_set(uint32_t val)
762 {
763  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, val);
764 }
765 
766 static INLINE uint32_t clk_enable_2_get(void)
767 {
768  return (RD_WORD(GLOBAL_REG_CLK_ENABLE_2));
769 }
770 
771 static INLINE void clk_enable_2_set(uint32_t val)
772 {
773  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, val);
774 }
775 
776 static INLINE uint32_t clk_ctl_1_get(void)
777 {
778  return (RD_WORD(GLOBAL_REG_CLK_CTRL_1));
779 }
780 
781 static INLINE void clk_ctl_1_set(uint32_t val)
782 {
783  WR_WORD(GLOBAL_REG_CLK_CTRL_1, val);
784 }
785 
786 static INLINE uint32_t clk_ctl_2_get(void)
787 {
788  return (RD_WORD(GLOBAL_REG_CLK_CTRL_2));
789 }
790 
791 static INLINE void clk_ctl_2_set(uint32_t val)
792 {
793  WR_WORD(GLOBAL_REG_CLK_CTRL_2, val);
794 }
795 
796 static INLINE void clk_tmr0_mux(int mux)
797 {
798  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
799  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_SHIFT);
800  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_SHIFT;
801  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_EMIT_SHM_IF_CLK_SEL | GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_CAP_SHM_IF_CLK_SEL);
802  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_EMIT_SHM_IF_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_EMIT_SHM_IF_CLK_SEL_SHIFT;
803  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_CAP_SHM_IF_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_CAP_SHM_IF_CLK_SEL_SHIFT;
804  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
805 }
806 
807 static INLINE void clk_tmr1_mux(int mux)
808 {
809  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
810  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_SHIFT);
811  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_SHIFT;
812  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
813 }
814 
815 static INLINE void clk_tmr2_mux(int mux)
816 {
817  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
818  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_SHIFT);
819  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_SHIFT;
820  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
821 }
822 
823 static INLINE void clk_tmr3_mux(int mux)
824 {
825  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
826  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_SHIFT);
827  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_SHIFT;
828  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
829 }
830 
831 static INLINE void clk_tmr4_mux(int mux)
832 {
833  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
834  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_SHIFT);
835  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_SHIFT;
836  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
837 }
838 
839 static INLINE void clk_tmr5_mux(int mux)
840 {
841  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
842  reg &= ~(GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_MASK << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_SHIFT);
843  reg |= (mux & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_SHIFT;
844  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
845 }
846 static INLINE void clk_tmr6_mux(int mux)
847 {
848  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
849  reg &= ~(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_MASK << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_SHIFT);
850  reg |= (mux & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_MASK) << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_SHIFT;
851  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, reg);
852 }
853 static INLINE void clk_tmr7_mux(int mux)
854 {
855  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
856  reg &= ~(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_MASK << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_SHIFT);
857  reg |= (mux & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_MASK) << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_SHIFT;
858  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, reg);
859 }
860 static INLINE void clk_tmr8_mux(int mux)
861 {
862  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
863  reg &= ~(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_MASK << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_SHIFT);
864  reg |= (mux & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_MASK) << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_SHIFT;
865  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, reg);
866 }
867 static INLINE void clk_tmr9_mux(int mux)
868 {
869  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
870  reg &= ~(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_MASK << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_SHIFT);
871  reg |= (mux & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_MASK) << GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_SHIFT;
872  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, reg);
873 }
874 static INLINE void clk_tmr_mux(int mux0, int mux1, int mux2, int mux3, int mux4, int mux5)
875 {
876  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
877  reg |= ((mux0 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_SHIFT)|
878  ((mux1 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_SHIFT)|
879  ((mux2 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_SHIFT)|
880  ((mux3 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_SHIFT)|
881  ((mux4 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_SHIFT)|
882  ((mux5 & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_MASK) << GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_SHIFT);
883  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, reg);
884 }
885 
886 static INLINE int clk_tmr0_mux_get(void)
887 {
888  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
889  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_SEL_MASK;
890  return mux;
891 }
892 
893 static INLINE int clk_tmr1_mux_get(void)
894 {
895  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
896  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_SEL_MASK;
897  return mux;
898 }
899 
900 static INLINE int clk_tmr2_mux_get(void)
901 {
902  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
903  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_SEL_MASK;
904  return mux;
905 }
906 
907 static INLINE int clk_tmr3_mux_get(void)
908 {
909  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
910  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_SEL_MASK;
911  return mux;
912 }
913 
914 static INLINE int clk_tmr4_mux_get(void)
915 {
916  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
917  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_SEL_MASK;
918  return mux;
919 }
920 
921 static INLINE int clk_tmr5_mux_get(void)
922 {
923  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL);
924  int mux = (reg >> GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_SEL_MASK;
925  return mux;
926 }
927 
928 static INLINE int clk_tmr6_mux_get(void)
929 {
930  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
931  int mux = (reg >> GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_SEL_MASK;
932  return mux;
933 }
934 
935 static INLINE int clk_tmr7_mux_get(void)
936 {
937  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
938  int mux = (reg >> GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_SEL_MASK;
939  return mux;
940 }
941 
942 static INLINE int clk_tmr8_mux_get(void)
943 {
944  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
945  int mux = (reg >> GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_SEL_MASK;
946  return mux;
947 }
948 
949 static INLINE int clk_tmr9_mux_get(void)
950 {
951  uint32_t reg = RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL);
952  int mux = (reg >> GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_SHIFT) & GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_SEL_MASK;
953  return mux;
954 }
955 
956 static INLINE uint32_t clk_tmr_mux_get(void)
957 {
958  return (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL) & 0xFFF);
959 }
960 
961 static INLINE void clk_tmr_mux_set(uint32_t mux)
962 {
963  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, mux);
964 }
965 
966 static INLINE void clk_slv_i2s_mux(int from_pad)
967 {
968  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
969 
970  if (from_pad) {
971  reg |= GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D0_I2S_SLAVE_SCLK_FROM_PAD;
972  } else {
973  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D0_I2S_SLAVE_SCLK_FROM_PAD;
974  }
975 
976  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
977 }
978 
979 static INLINE void clk_smem_mux(uint32_t clk_div)
980 {
981  WR_WORD(GLOBAL_REG_CLK_CTRL_1, ((RD_WORD(GLOBAL_REG_CLK_CTRL_1) & ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_SHM_CLK) | ((clk_div & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_SHM_CLK_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_SHM_CLK_SHIFT) ));
982 }
983 
984 static INLINE uint32_t clk_smem_mux_get(void)
985 {
986  return ((RD_WORD(GLOBAL_REG_CLK_CTRL_1) & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_SHM_CLK) >> GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_SHM_CLK_SHIFT);
987 }
988 
989 static INLINE void clk_mi2s_divider(int en)
990 {
991  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
992  if (en) {
993  reg |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_I2S_INT_DIV_INPUT_CLK;
994  } else {
995  reg &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_I2S_INT_DIV_INPUT_CLK;
996  }
997  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, reg);
998 }
999 
1000 static INLINE void clk_mi2s(uint32_t div)
1001 {
1002  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_2);
1003 
1004  reg &= ~GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_INT_DIV_VALUE;
1005  reg |= ((div & GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_INT_DIV_VALUE_MASK) << GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_INT_DIV_VALUE_SHIFT);
1006 
1007  WR_WORD(GLOBAL_REG_CLK_CTRL_2, reg);
1008 }
1009 
1010 static INLINE void clk_qspi_mux(uint32_t div)
1011 {
1012 #if !CFG_FPGA
1013  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_2);
1014 
1015  reg &= ~GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_SEL_SSIMAS0_CLK;
1016  reg |= ((div & GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_SEL_SSIMAS0_CLK_MASK) << GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_SEL_SSIMAS0_CLK_SHIFT);
1017 
1018  WR_WORD(GLOBAL_REG_CLK_CTRL_2, reg);
1019 #endif
1020 }
1021 
1022 static INLINE uint32_t clk_qspi_mux_get(void)
1023 {
1024  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_2);
1025 
1026  return ((reg & GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_SEL_SSIMAS0_CLK) >> GLOBAL_REG_CLK_CTRL_2_CTL_CLK_CTRL_2_SEL_SSIMAS0_CLK_SHIFT);
1027 }
1028 
1029 static INLINE void clk_efuse_mux(uint32_t div)
1030 {
1031  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
1032 
1033  if (div == CLK_EFUSE_DIV4) {
1034  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_EFUSE_CLK;
1035  } else {
1036  reg |= GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_EFUSE_CLK;
1037  }
1038 
1039  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
1040 }
1041 
1042 static INLINE uint32_t clk_efuse_mux_get(void)
1043 {
1044  return ((RD_WORD(GLOBAL_REG_CLK_CTRL_1) & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_EFUSE_CLK) ? 1 : 0 );
1045 }
1046 
1047 static INLINE void clk_kb_en(int en)
1048 {
1049  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1050  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1051 
1052  if (en) {
1053  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_KEYBOARD_CLK_FREE|GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_KEYBOARD_CLK_GATED;
1054  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_KEYBOARD_TOP_PCLK;
1055  } else {
1056  reg &= ~(GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_KEYBOARD_CLK_FREE|GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_KEYBOARD_CLK_GATED);
1057  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_KEYBOARD_TOP_PCLK;
1058  }
1059  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1060  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1061 }
1062 
1063 static INLINE void clk_hash_en(int en)
1064 {
1065  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1066 
1067  if (en) {
1068  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1069  } else {
1070  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1071  }
1072  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1073 }
1074 
1075 static INLINE void clk_ecc_en(int en)
1076 {
1077  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1078  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1079 
1080  if (en) {
1081  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1082  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_FW_RAM_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_A_CLK|
1083  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_B_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_C_CLK|
1084  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_D_CLK;
1085  } else {
1086  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1087  reg1 &= ~(GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_FW_RAM_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_A_CLK|
1088  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_B_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_C_CLK|
1089  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_D_CLK);
1090  }
1091  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1092  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1093 }
1094 
1095 static INLINE void clk_aes_en(int en)
1096 {
1097  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1098  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1099 
1100  if (en) {
1101  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1102  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_FW_RAM_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_A_CLK|
1103  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_B_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_C_CLK|
1104  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_D_CLK;
1105  } else {
1106  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SECURITY_CORE_PCLK;
1107  reg1 &= ~(GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_FW_RAM_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_A_CLK|
1108  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_B_CLK|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_C_CLK|
1109  GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_ECC_MEM_D_CLK);
1110  }
1111  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1112  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1113 }
1114 
1115 static INLINE void clk_mspi_en(int en)
1116 {
1117  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1118  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1119 
1120  if (en) {
1121  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_MASTER1_SSI_CLK;
1122  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_MASTER1_PCLK;
1123  } else {
1124  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_MASTER1_SSI_CLK;
1125  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_MASTER1_PCLK;
1126  }
1127  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1128  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1129 }
1130 
1131 static INLINE void clk_sspi0_en(int en)
1132 {
1133  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1134  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1135 
1136  if (en) {
1137  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_SLAVE0_SSI_CLK;
1138  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_SLAVE0_PCLK;
1139  } else {
1140  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_SLAVE0_SSI_CLK;
1141  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_SLAVE0_PCLK;
1142  }
1143  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1144  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1145 }
1146 
1147 static INLINE void clk_sspi1_en(int en)
1148 {
1149  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1150  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1151 
1152  if (en) {
1153  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_SLAVE1_SSI_CLK;
1154  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_SLAVE1_PCLK;
1155  } else {
1156  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_SSI_SLAVE1_SSI_CLK;
1157  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SSI_SLAVE1_PCLK;
1158  }
1159  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1160  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1161 }
1162 
1163 static INLINE void clk_intr_ctl_en(int en)
1164 {
1165  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1166 
1167  if (en) {
1168  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_INTRCTRL_CLK;
1169  } else {
1170  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_INTRCTRL_CLK;
1171  }
1172  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1173 }
1174 
1175 static INLINE void clk_wdt_en(int en)
1176 {
1177  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1178  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1179 
1180  if (en) {
1181  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_WDT_TCLK;
1182  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_WDT_PCLK;
1183  } else {
1184  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_WDT_TCLK;
1185  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_WDT_PCLK;
1186  }
1187  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1188  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1189 }
1190 
1191 static INLINE void clk_i2c0_en(int en)
1192 {
1193  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1194  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1195 
1196  if (en) {
1197  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2C_0_IC_CLK;
1198  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2C_0_PCLK;
1199  } else {
1200  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2C_0_IC_CLK;
1201  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2C_0_PCLK;
1202  }
1203  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1204  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1205 }
1206 
1207 static INLINE void clk_i2c1_en(int en)
1208 {
1209  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1210  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1211 
1212  if (en) {
1213  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2C_1_IC_CLK;
1214  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2C_1_PCLK;
1215  } else {
1216  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2C_1_IC_CLK;
1217  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2C_1_PCLK;
1218  }
1219  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1220  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1221 }
1222 
1223 static INLINE void clk_efuse_en(int en)
1224 {
1225  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1226  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1227 
1228  if (en) {
1229  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_EFUSE_CLK;
1230  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_EFUSECTRL_TOP_PCLK;
1231  } else {
1232  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_EFUSE_CLK;
1233  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_EFUSECTRL_TOP_PCLK;
1234  }
1235  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1236  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1237 }
1238 
1239 static INLINE void clk_tmr_pclk_en(void)
1240 {
1241  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, (RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2)|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_TIMERS_0_PCLK));
1242 }
1243 static INLINE void clk_tmr_pclk_dis(void)
1244 {
1245  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, (RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2)&(~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_TIMERS_0_PCLK)));
1246 }
1247 static INLINE void clk_tmr0_en(void)
1248 {
1249  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_ENABLE));
1250 }
1251 
1252 static INLINE void clk_tmr0_dis(void)
1253 {
1254  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_ENABLE));
1255 }
1256 
1257 static INLINE void clk_tmr0_emit_en(void)
1258 {
1259  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_EMIT_ENABLE));
1260 }
1261 
1262 static INLINE void clk_tmr0_emit_dis(void)
1263 {
1264  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_EMIT_ENABLE));
1265 }
1266 
1267 static INLINE void clk_tmr0_capture_en(void)
1268 {
1269  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_CAP_ENABLE));
1270 }
1271 
1272 static INLINE void clk_tmr0_capture_dis(void)
1273 {
1274  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_0_CLK_CAP_ENABLE));
1275 }
1276 
1277 static INLINE void clk_tmr0_smem_emit_en(void)
1278 {
1279  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_EMIT_SHM_IF_ENABLE));
1280 }
1281 
1282 static INLINE void clk_tmr0_smem_emit_dis(void)
1283 {
1284  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_EMIT_SHM_IF_ENABLE));
1285 }
1286 
1287 static INLINE void clk_tmr0_smem_capture_en(void)
1288 {
1289  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_CAP_SHM_IF_ENABLE));
1290 }
1291 
1292 static INLINE void clk_tmr0_smem_capture_dis(void)
1293 {
1294  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_CAP_SHM_IF_ENABLE));
1295 }
1296 
1297 static INLINE void clk_tmr1_en(void)
1298 {
1299  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_ENABLE));
1300 }
1301 
1302 static INLINE void clk_tmr1_dis(void)
1303 {
1304  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_ENABLE));
1305 }
1306 
1307 static INLINE void clk_tmr1_emit_en(void)
1308 {
1309  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_EMIT_ENABLE));
1310 }
1311 
1312 static INLINE void clk_tmr1_emit_dis(void)
1313 {
1314  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_EMIT_ENABLE));
1315 }
1316 
1317 static INLINE void clk_tmr1_capture_en(void)
1318 {
1319  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_CAP_ENABLE));
1320 }
1321 
1322 static INLINE void clk_tmr1_capture_dis(void)
1323 {
1324  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_1_CLK_CAP_ENABLE));
1325 }
1326 
1327 static INLINE void clk_tmr2_en(void)
1328 {
1329  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_ENABLE));
1330 }
1331 
1332 static INLINE void clk_tmr2_dis(void)
1333 {
1334  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_2_CLK_ENABLE));
1335 }
1336 
1337 static INLINE void clk_tmr3_en(void)
1338 {
1339  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_ENABLE));
1340 }
1341 
1342 static INLINE void clk_tmr3_dis(void)
1343 {
1344  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_3_CLK_ENABLE));
1345 }
1346 
1347 static INLINE void clk_tmr4_en(void)
1348 {
1349  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_ENABLE));
1350 }
1351 
1352 static INLINE void clk_tmr4_dis(void)
1353 {
1354  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_4_CLK_ENABLE));
1355 }
1356 
1357 static INLINE void clk_tmr5_en(void)
1358 {
1359  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)|GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_ENABLE));
1360 }
1361 
1362 static INLINE void clk_tmr5_dis(void)
1363 {
1364  WR_WORD(GLOBAL_REG_TIMER_CLK_CTRL, (RD_WORD(GLOBAL_REG_TIMER_CLK_CTRL)&~GLOBAL_REG_TIMER_CLK_CTRL_CTL_PD1_TIMER_5_CLK_ENABLE));
1365 }
1366 
1367 static INLINE void clk_tmr6_en(void)
1368 {
1369  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_ENABLE));
1370 }
1371 
1372 static INLINE void clk_tmr6_dis(void)
1373 {
1374  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_ENABLE));
1375 }
1376 
1377 static INLINE void clk_tmr6_emit_en(void)
1378 {
1379  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_EMIT_ENABLE));
1380 }
1381 
1382 static INLINE void clk_tmr6_emit_dis(void)
1383 {
1384  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_EMIT_ENABLE));
1385 }
1386 
1387 static INLINE void clk_tmr6_capture_en(void)
1388 {
1389  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_CAP_ENABLE));
1390 }
1391 
1392 static INLINE void clk_tmr6_capture_dis(void)
1393 {
1394  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_0_CLK_CAP_ENABLE));
1395 }
1396 
1397 static INLINE void clk_tmr7_en(void)
1398 {
1399  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_ENABLE));
1400 }
1401 
1402 static INLINE void clk_tmr7_dis(void)
1403 {
1404  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_1_CLK_ENABLE));
1405 }
1406 
1407 static INLINE void clk_tmr8_en(void)
1408 {
1409  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_ENABLE));
1410 }
1411 
1412 static INLINE void clk_tmr8_dis(void)
1413 {
1414  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_2_CLK_ENABLE));
1415 }
1416 
1417 static INLINE void clk_tmr9_en(void)
1418 {
1419  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)|GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_ENABLE));
1420 }
1421 
1422 static INLINE void clk_tmr9_dis(void)
1423 {
1424  WR_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL, (RD_WORD(GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL)&~GLOBAL_REG_TIMER_ADDITIONAL_CLK_RST_CTRL_CTL_PD1_TIMER_ADD_3_CLK_ENABLE));
1425 }
1426 static INLINE void clk_pwm_en(int en)
1427 {
1428  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1429 
1430  if (en) {
1431  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_PWM0_PCLK;
1432  } else {
1433  reg &= ~ GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_PWM0_PCLK;
1434  }
1435 
1436  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1437 }
1438 
1439 static INLINE void clk_counter_en(int en)
1440 {
1441  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1442  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
1443  if (en) {
1444  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_COUNTER_TOP_PCLK;
1445  reg1 |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_32M_CLK|
1446  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_16M_CLK|
1447  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_8M_CLK;
1448  } else {
1449  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_COUNTER_TOP_PCLK;
1450  reg1 &= ~(GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_32M_CLK|
1451  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_16M_CLK|
1452  GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ENABLE_COUNTER_CLKRSTGEN_8M_CLK);
1453  }
1454 
1455  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1456  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, reg1);
1457 }
1458 
1459 static INLINE void clk_audio_en(int en)
1460 {
1461  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1462  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1463 
1464  if (en) {
1465  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_64M_CLK;
1466  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_AUDIO_TOP_PCLK;
1467  } else {
1468  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_64M_CLK;
1469  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_AUDIO_TOP_PCLK;
1470  }
1471 
1472  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1473  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1474 }
1475 
1476 static INLINE void clk_audio_enc_en(int en)
1477 {
1478  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1479 
1480  if (en) {
1481  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AURX_CLK;
1482  } else {
1483  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AURX_CLK;
1484  }
1485  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1486 }
1487 
1488 static INLINE void clk_audio_dec_en(int en)
1489 {
1490  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1491 
1492  if (en) {
1493  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AUTX_CLK|
1494  GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_SPK_CLK|
1495  GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_SD_CLK; // Sigma Delta;
1496  } else {
1497  reg &= ~(GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AUTX_CLK|
1498  GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_SPK_CLK |
1499  GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_SD_CLK);
1500  }
1501 
1502  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1503 }
1504 
1505 static INLINE void clk_audio_resample(int en)
1506 {
1507  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1508 
1509  if (en) {
1510  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AUTX_CLK;
1511  } else {
1512  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_AUDIO_AUTX_CLK;
1513  }
1514 
1515  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1516 }
1517 
1518 
1519 static INLINE void clk_audio_sdm_mux(uint32_t mux)
1520 {
1521  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_CTRL_1);
1522 
1523  reg &= ~GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D0_AUDIO_SPK_SD_CLK;
1524  reg |= ((mux & GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D0_AUDIO_SPK_SD_CLK_MASK) << GLOBAL_REG_CLK_CTRL_1_CTL_CLK_CTRL_1_SEL_D0_AUDIO_SPK_SD_CLK_SHIFT);
1525 
1526  WR_WORD(GLOBAL_REG_CLK_CTRL_1, reg);
1527 }
1528 
1529 static INLINE void clk_sadc_en(int en)
1530 {
1531  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1532  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1533 
1534  if (en) {
1535  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SADC_CLK;
1536  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SADCCTRL_TOP_PCLK;
1537  } else {
1538  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SADC_CLK;
1539  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SADCCTRL_TOP_PCLK;
1540  }
1541 
1542  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1543  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1544 }
1545 
1546 static INLINE void clk_mi2s_en(int en)
1547 {
1548  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1549  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1550 
1551  if (en) {
1552  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2S_MASTER_SCLK;
1553  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2S_MASTER_PCLK;
1554  } else {
1555  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2S_MASTER_SCLK;
1556  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2S_MASTER_PCLK;
1557  }
1558 
1559  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1560  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1561 }
1562 
1563 static INLINE void clk_si2s_en(int en)
1564 {
1565  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1566  uint32_t reg1 = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1567 
1568  if (en) {
1569  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2S_SLAVE_SCLK;
1570  reg1 |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2S_SLAVE_PCLK;
1571  } else {
1572  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_CPU_I_I2S_SLAVE_SCLK;
1573  reg1 &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_I2S_SLAVE_PCLK;
1574  }
1575 
1576  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1577  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg1);
1578 }
1579 
1580 static INLINE void clk_quaddec_en(int en)
1581 {
1582  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1583 
1584  if (en) {
1585  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_CLK_QUADDEC|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_QUADDEC_TOP_PCLK;
1586  } else {
1587  reg &= ~(GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_CLK_QUADDEC|GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_QUADDEC_TOP_PCLK);
1588  }
1589 
1590  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1591 }
1592 
1593 static INLINE void clk_dma_en(int en)
1594 {
1595  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1596 
1597  if (en) {
1598  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_DMAC_REQ_MUX_PCLK;
1599  } else {
1600  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_DMAC_REQ_MUX_PCLK;
1601  }
1602 
1603  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1604 }
1605 
1606 static INLINE void clk_uart0_en(int en)
1607 {
1608  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1609 
1610  if (en) {
1611  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_UART_0_PCLK;
1612  } else {
1613  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_UART_0_PCLK;
1614  }
1615 
1616  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1617 }
1618 
1619 static INLINE void clk_uart1_en(int en)
1620 {
1621  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1622 
1623  if (en) {
1624  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_UART_1_PCLK;
1625  } else {
1626  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_UART_1_PCLK;
1627  }
1628 
1629  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1630 }
1631 
1632 static INLINE void clk_sm_0_en(int en)
1633 {
1634  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1635 
1636  if (en)
1637  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_0_CLK;
1638  else
1639  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_0_CLK;
1640 
1641  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1642 }
1643 
1644 static INLINE void clk_sm_1_en(int en)
1645 {
1646  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1647 
1648  if (en)
1649  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_1_CLK;
1650  else
1651  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_1_CLK;
1652 
1653  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1654 }
1655 
1656 static INLINE void clk_sm_2_en(int en)
1657 {
1658  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1659 
1660  if (en)
1661  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_2_CLK;
1662  else
1663  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_2_CLK;
1664 
1665  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1666 }
1667 
1668 static INLINE void clk_sm_3_en(int en)
1669 {
1670  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1671 
1672  if (en)
1673  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_3_CLK;
1674  else
1675  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_3_CLK;
1676 
1677  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1678 }
1679 
1680 static INLINE void clk_sm_4_en(int en)
1681 {
1682  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1683 
1684  if (en)
1685  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_4_CLK;
1686  else
1687  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_SHM_MEM_4_CLK;
1688 
1689  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1690 }
1691 
1692 static INLINE void clk_sm_en(int en)
1693 {
1694  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1695 
1696  if (en) {
1697  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_SHAREDMEM_TOP_CLK|GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_AHB2SHM_HCLK;
1698  } else {
1699  reg &= ~(GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_SHAREDMEM_TOP_CLK|GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_AHB2SHM_HCLK);
1700  }
1701 
1702  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1703 }
1704 
1705 static INLINE void clk_ble_en(int en)
1706 {
1707 #if 0
1708  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
1709  if (en) {
1710  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_RXTX_SEQ_REGS_CLK;
1711  } else {
1712  reg &= ~GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_RXTX_SEQ_REGS_CLK;
1713  }
1714  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
1715 
1716  reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_2);
1717  if (en) {
1718  reg |= GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_CLK_EM;
1719  } else {
1720  reg &= ~GLOBAL_REG_CLKD0_ENABLE_2_CTL_CLKD0_ENABLE_2_CLK_EM;
1721  }
1722  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_2, reg);
1723 
1724 
1725  reg = RD_WORD(GLOBAL_REG_CLKD1_ENABLE_1);
1726  if (en) {
1727  reg |= GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_AHBTRG_TOP_PCLK|
1728  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_MDM_CORE_CLK|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_MDM_PCLK|
1729  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_CLK_ANT|
1730  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_BB_MASTER1_GCLK|
1731  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_CLK_PLLTRIG_MEM|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_PCLK_PLLTRIG|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_PLLTRIG|
1732  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_CPU_I_CLK_AHBTRG|
1733  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_MAIN_CLK|
1734  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_MAIN_CLK_FREE|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_CNTR_CLK|
1735  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_BLE_FE_PCLK;
1736  } else {
1737  reg &= ~(GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_AHBTRG_TOP_PCLK|
1738  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_MDM_CORE_CLK|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_MDM_PCLK|
1739  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_CLK_ANT|
1740  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_1_BLE_I_BB_MASTER1_GCLK|
1741  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_CLK_PLLTRIG_MEM|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_PCLK_PLLTRIG|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_PLLTRIG|
1742  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_CPU_I_CLK_AHBTRG|
1743  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_MAIN_CLK|
1744  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_MAIN_CLK_FREE|GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_TRXSEQ_I_CNTR_CLK|
1745  GLOBAL_REG_CLKD1_ENABLE_1_CTL_CLKD1_ENABLE_BLE_FE_PCLK);
1746  }
1747  WR_WORD(GLOBAL_REG_CLKD1_ENABLE_1, reg);
1748 
1749  reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1750  if (en)
1751  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_CLK_EM2SHM;
1752  else
1753  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_CLK_EM2SHM;
1754  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1755 #endif
1756 }
1757 
1758 static INLINE void clk_calib_en(int en)
1759 {
1760  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_2);
1761  if (en) {
1762  reg |= GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN_FOR_CALIB;
1763  } else {
1764  reg &= ~GLOBAL_REG_CLK_ENABLE_2_CTL_CLK_ENABLE_2_ROOT_XO_TO_DIGI_CLK_EN_FOR_CALIB;
1765  }
1766  WR_WORD(GLOBAL_REG_CLK_ENABLE_2, reg);
1767 }
1768 
1769 static INLINE void clk_ipm_en(int en)
1770 {
1771  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1772 
1773  if (en) {
1774  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_IPM_FREE;
1775  } else {
1776  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_IPM_FREE;
1777  }
1778 
1779  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1780 }
1781 
1782 static INLINE void clk_trig_en(int en)
1783 {
1784  uint32_t reg = RD_WORD(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL);
1785  uint32_t reg2 = RD_WORD(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_2);
1786  uint32_t reg_clk_ctrl4 = RD_WORD(GLOBAL_REG_CLK_CTRL_4);
1787  if (en) {
1788  reg |= GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_TRIGHDLR_PCLK_EN|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_TRIGHDLR_CLK_FREE_EN;
1789 
1790 
1791  reg &= ~(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_CLK_FREE|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_SHM_CLK|
1792  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MEM_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HP_CLK|
1793  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MP_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_LP_CLK|
1794  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HP_TIMER_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MP_TIMER_CLK|
1795  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_LP_TIMER_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HCLK);
1796  reg2 &= ~GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_2_CTL_WFI_GATE_TRIGHDLR_APB_MSTR_PCLK;
1797  reg_clk_ctrl4 &= ~(GLOBAL_REG_CLK_CTRL_4_CTL_CLK_CTRL_4_DIS_CLK_WFI_APB_D0_1_HCLK|GLOBAL_REG_CLK_CTRL_4_CTL_CLK_CTRL_4_DIS_CLK_WFI_APB_D0_2_HCLK);
1798  } else {
1799  reg &= ~(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_TRIGHDLR_PCLK_EN|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_TRIGHDLR_CLK_FREE_EN);
1800 
1801  reg |= (GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_CLK_FREE|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_SHM_CLK|
1802  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MEM_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HP_CLK|
1803  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MP_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_LP_CLK|
1804  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HP_TIMER_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_MP_TIMER_CLK|
1805  GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_LP_TIMER_CLK|GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_CTL_WFI_GATE_TRIGHDLR_HCLK);
1806  reg2 |= GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_2_CTL_WFI_GATE_TRIGHDLR_APB_MSTR_PCLK;
1807  reg_clk_ctrl4 |= (GLOBAL_REG_CLK_CTRL_4_CTL_CLK_CTRL_4_DIS_CLK_WFI_APB_D0_1_HCLK|GLOBAL_REG_CLK_CTRL_4_CTL_CLK_CTRL_4_DIS_CLK_WFI_APB_D0_2_HCLK);
1808  }
1809 
1810  WR_WORD(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL, reg);
1811  WR_WORD(GLOBAL_REG_TRIGHDLR_CLK_RST_CTRL_2, reg2);
1812  WR_WORD(GLOBAL_REG_CLK_CTRL_4, reg_clk_ctrl4);
1813 }
1814 
1815 static INLINE void clk_wfi_clean(void)
1816 {
1817  uint32_t reg_clk_ctrl4 = RD_WORD(GLOBAL_REG_CLK_CTRL_4);
1818 
1819  reg_clk_ctrl4 &= ~(GLOBAL_REG_CLK_CTRL_4_CTL_CLK_CTRL_4_DIS_CLK_WFI_CALIB_REG_CLK);
1820 
1821  WR_WORD(GLOBAL_REG_CLK_CTRL_4, reg_clk_ctrl4);
1822 }
1823 
1824 static INLINE void clk_gpio_0_intr_en(int en)
1825 {
1826  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1827 
1828  if (en) {
1829  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_0_INTR_CLK;
1830  } else {
1831  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_0_INTR_CLK;
1832  }
1833 
1834  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1835 }
1836 
1837 static INLINE void clk_gpio_1_intr_en(int en)
1838 {
1839  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1840 
1841  if (en) {
1842  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_1_INTR_CLK;
1843  } else {
1844  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_1_INTR_CLK;
1845  }
1846 
1847  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1848 }
1849 
1850 static INLINE void clk_gpio_2_intr_en(int en)
1851 {
1852  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1853 
1854  if (en) {
1855  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_2_INTR_CLK;
1856  } else {
1857  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_2_INTR_CLK;
1858  }
1859 
1860  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1861 }
1862 
1863 static INLINE void clk_gpio_3_intr_en(int en)
1864 {
1865  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1866 
1867  if (en) {
1868  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_3_INTR_CLK;
1869  } else {
1870  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_3_INTR_CLK;
1871  }
1872 
1873  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1874 }
1875 
1876 static INLINE void clk_gpio_4_intr_en(int en)
1877 {
1878  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1879 
1880  if (en) {
1881  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_4_INTR_CLK;
1882  } else {
1883  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_GPIO_4_INTR_CLK;
1884  }
1885 
1886  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1887 }
1888 
1889 static INLINE void clk_wdt_intr_en(int en)
1890 {
1891  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1892 
1893  if (en) {
1894  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
1895  } else {
1896  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
1897  }
1898 
1899  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1900 }
1901 
1902 static INLINE void clk_sw_intr_en(int en)
1903 {
1904  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1905 
1906  if (en) {
1907  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_SW_INTR_CLK;
1908  } else {
1909  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_SW_INTR_CLK;
1910  }
1911 
1912  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1913 }
1914 
1915 static INLINE void clk_nmi_intr_en(int en)
1916 {
1917  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
1918 
1919  if (en) {
1920  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_NMI_CLK;
1921  } else {
1922  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_NMI_CLK;
1923  }
1924 
1925  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
1926 }
1927 
1928 
1929 static INLINE void clk_rtc_cap(uint8_t cap)
1930 {
1931  // RTC cap only have 5 bits
1932  cap &= 0x1F;
1933  WR_WORD(AON_REG_PMU_AONPD_REG_5TO6, (cap << 4) | (cap << 9) | 0xF);
1934 }
1935 
1936 static FORCEINLINE void clk_rtc_en(void)
1937 {
1938  WR_WORD(AON_REG_PMU_MISC_CTRL, (RD_WORD(AON_REG_PMU_MISC_CTRL)|AON_REG_PMU_MISC_CTRL_CTL_CLK_32K_RTC_EN));
1939 }
1940 
1941 static FORCEINLINE void clk_rtc_dis(void)
1942 {
1943  WR_WORD(AON_REG_PMU_MISC_CTRL, (RD_WORD(AON_REG_PMU_MISC_CTRL)&~AON_REG_PMU_MISC_CTRL_CTL_CLK_32K_RTC_EN));
1944 }
1945 
1946 static FORCEINLINE void clk_32k_rtc(void)
1947 {
1948  WR_WORD(AON_REG_AON_MISC_CTRL, (RD_WORD(AON_REG_AON_MISC_CTRL)|AON_REG_AON_MISC_CTRL_AON_MISC_CTRL_SEL_AON_32K_CLK));
1949 }
1950 
1951 static FORCEINLINE void clk_32k_rc(void)
1952 {
1953  WR_WORD(AON_REG_AON_MISC_CTRL, (RD_WORD(AON_REG_AON_MISC_CTRL)&~AON_REG_AON_MISC_CTRL_AON_MISC_CTRL_SEL_AON_32K_CLK));
1954 }
1955 
1956 static FORCEINLINE void clk_wdt_rtc(void)
1957 {
1958  WR_WORD(AON_REG_AON_MISC_CTRL, (RD_WORD(AON_REG_AON_MISC_CTRL)|(AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK|AON_REG_AON_MISC_CTRL_CTL_WDT_RST_SWITCH_RC_CLK)));
1959 }
1960 
1961 static FORCEINLINE void clk_wdt_rc(void)
1962 {
1963  WR_WORD(AON_REG_AON_MISC_CTRL, (RD_WORD(AON_REG_AON_MISC_CTRL)&~AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK));
1964 }
1965 
1966 static INLINE void clk_force_spiflash_ctl_clk(void)
1967 {
1968  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_1);
1969  reg |= GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_SPIFLASH_CTRL_CLK;
1970  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_1, reg);
1971 }
1972 
1973 static INLINE void clk_force_dma_ctl_clks(int force_on)
1974 {
1975 #if 0
1976  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_1);
1977  if (force_on) {
1978  reg |= GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_AHB_D0_HCLK|
1979  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_1_HCLK|
1980  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_2_HCLK|
1981  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_3_HCLK|
1982  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_ICM_DATA_CODE_RAM_CLK|
1983  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DATA_CODE_SRAM_A_CLK|
1984  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DATA_CODE_SRAM_B_CLK|
1985  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DMAC_REQ_MUX_CLK;
1986  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_1, reg);
1987  reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_2);
1988  reg |= GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_0_CLK|
1989  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_1_CLK|
1990  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_2_CLK|
1991  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_3_CLK|
1992  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_4_CLK|
1993  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DMAC_0_CLK|
1994  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DMAC_1_CLK|
1995  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_D2_M2_AHB_HCLK;
1996  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_2, reg);
1997  reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_3);
1998  reg |= GLOBAL_REG_CLK_FORCE_ON_3_CTL_CLK_FORCE_ON_3_DC_RAM_64_80K_CLK;
1999  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_3, reg);
2000  } else {
2001  reg &= ~(GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_AHB_D0_HCLK|
2002  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_1_HCLK|
2003  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_2_HCLK|
2004  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_APB_D0_3_HCLK|
2005  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_ICM_DATA_CODE_RAM_CLK|
2006  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DATA_CODE_SRAM_A_CLK|
2007  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DATA_CODE_SRAM_B_CLK|
2008  GLOBAL_REG_CLK_FORCE_ON_1_CTL_CLK_FORCE_ON_1_DMAC_REQ_MUX_CLK);
2009  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_1, reg);
2010  reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_2);
2011  reg &= ~(GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_0_CLK|
2012  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_1_CLK|
2013  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_2_CLK|
2014  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_3_CLK|
2015  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DC_RAM_4_CLK|
2016  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DMAC_0_CLK|
2017  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_DMAC_1_CLK|
2018  GLOBAL_REG_CLK_FORCE_ON_2_CTL_CLK_FORCE_ON_2_D2_M2_AHB_HCLK);
2019  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_2, reg);
2020  reg = RD_WORD(GLOBAL_REG_CLK_FORCE_ON_3);
2021  reg &= ~GLOBAL_REG_CLK_FORCE_ON_3_CTL_CLK_FORCE_ON_3_DC_RAM_64_80K_CLK;
2022  WR_WORD(GLOBAL_REG_CLK_FORCE_ON_3, reg);
2023  }
2024 #endif
2025 }
2026 
2027 static INLINE void clk_reset_ble_sleep_clk(void)
2028 {
2029 #if 0
2030  WR_WORD(AON_REG_AON_RESET_CTRL, 0x1d); //Reset
2031  WR_WORD(AON_REG_AON_RESET_CTRL, 0x1f);
2032 #endif
2033 }
2034 
2035 static FORCEINLINE void clk_ble_time_snap_shot(void)
2036 {
2037  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_SNAPSHOT_BLE_BB_CNTR);
2038  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
2039 }
2040 
2041 static FORCEINLINE uint32_t clk_ble_time_clkn(void)
2042 {
2043  return RD_WORD(GLOBAL2_REG_SNAPSHOT_VAL_BLE_CLKN);
2044 }
2045 
2046 static FORCEINLINE uint32_t clk_ble_time_fine(void)
2047 {
2048  return RD_WORD(GLOBAL2_REG_SNAPSHOT_VAL_BLE_FINE);
2049 }
2050 
2051 static INLINE void clk_32k_calib(uint8_t cycles)
2052 {
2053  uint32_t reg;
2054  reg = ((cycles & GLOBAL_REG_CALIBRATION_MISC_CTRL_CTL_CAL_CNT_LMT_LOG2_MASK) << GLOBAL_REG_CALIBRATION_MISC_CTRL_CTL_CAL_CNT_LMT_LOG2_SHIFT);
2055  reg |= GLOBAL_REG_CALIBRATION_MISC_CTRL_CTL_CAL_START;
2056 
2057  WR_WORD(GLOBAL_REG_CALIBRATION_MISC_CTRL, reg); // start the calibration
2058 }
2059 
2060 static INLINE uint32_t clk_32k_calib_get(void)
2061 {
2062  return (RD_WORD(GLOBAL_REG_CALIBRATION_MISC_STATUS) & (GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_INT|GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_FRAC));
2063 }
2064 
2065 static INLINE uint32_t clk_32k_calib_get_frac(void)
2066 {
2067  return ((RD_WORD(GLOBAL_REG_CALIBRATION_MISC_STATUS) & GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_FRAC) >> GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_FRAC_SHIFT);
2068 }
2069 
2070 static INLINE uint32_t clk_32k_calib_get_int(void)
2071 {
2072  return ((RD_WORD(GLOBAL_REG_CALIBRATION_MISC_STATUS) & GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_INT) >> GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_INT_SHIFT);
2073 }
2074 
2075 static INLINE int clk_32k_calib_done(void)
2076 {
2077  return ((RD_WORD(GLOBAL_REG_CALIBRATION_MISC_STATUS) & GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_DONE) ? 1 : 0);
2078 }
2079 
2080 static INLINE void clk_32k_calib_done_clear(void)
2081 {
2082  WR_WORD(GLOBAL_REG_CALIBRATION_MISC_STATUS, GLOBAL_REG_CALIBRATION_MISC_STATUS_STS_CALIB_COUNT_DONE);
2083 }
2084 
2085 static INLINE void clk_32k_hw_timing_corr(uint32_t corr)
2086 {
2087  WR_WORD(GLOBAL2_REG_HW_TIMING_CORR_CTRL, corr);
2088 }
2089 
2090 static INLINE void clk_ble_phase_match_reset(void)
2091 {
2092  uint32_t reg = RD_WORD(GLOBAL_REG_BLE_ADDITIONAL_CONTROL);
2093  // reset ble clk phases
2094  reg |= GLOBAL_REG_BLE_ADDITIONAL_CONTROL_CTL_BLE_PHASE_MATCH_SOFT_RESET;
2095  WR_WORD(GLOBAL_REG_BLE_ADDITIONAL_CONTROL, reg);
2096  //WR_WORD(GLOBAL_REG_BLE_ADDITIONAL_CONTROL, reg);
2097  //WR_WORD(GLOBAL_REG_BLE_ADDITIONAL_CONTROL, reg);
2098  reg &= ~GLOBAL_REG_BLE_ADDITIONAL_CONTROL_CTL_BLE_PHASE_MATCH_SOFT_RESET;
2099  WR_WORD(GLOBAL_REG_BLE_ADDITIONAL_CONTROL, reg);
2100 }
2101 
2102 static FORCEINLINE void clk_systick_mux(int mux)
2103 {
2104  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, ((RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL) & ~GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_SEL)|((mux & GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_SEL_MASK) << GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_SEL_SHIFT)));
2105 }
2106 
2107 static INLINE int clk_systick_mux_get(void)
2108 {
2109  return ((RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL) >> GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_SEL_SHIFT) & GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_SEL_MASK) ;
2110 }
2111 
2112 static FORCEINLINE void clk_systick_en(void)
2113 {
2114  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, (RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL)|GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_ENABLE));
2115 }
2116 
2117 static FORCEINLINE void clk_systick_dis(void)
2118 {
2119  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, (RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL)&~GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_ENABLE));
2120 }
2121 
2122 static INLINE void clk_systick_emit_en(int en)
2123 {
2124  uint32_t reg = RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL);
2125 
2126  if (en) {
2127  reg |= GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_EMIT_ENABLE;
2128  } else {
2129  reg &= ~GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_EMIT_ENABLE;
2130  }
2131 
2132  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, reg);
2133 }
2134 
2135 static INLINE void clk_systick_capture_en(int en)
2136 {
2137  uint32_t reg = RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL);
2138 
2139  if (en) {
2140  reg |= GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_CAP_ENABLE;
2141  } else {
2142  reg &= ~GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CLK_CAP_ENABLE;
2143  }
2144 
2145  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, reg);
2146 }
2147 
2148 static INLINE void clk_systick_force(int on)
2149 {
2150  uint32_t reg = RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL);
2151 
2152  if (on) {
2153  reg |= GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CNT_CLK_FORCE_ON;
2154  } else {
2155  reg |= GLOBAL_REG_SYSTICK_CLK_CTRL_CTL_SYSTICK_CNT_CLK_FORCE_OFF;
2156  }
2157  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, reg);
2158 }
2159 
2160 static INLINE uint32_t clk_systick_get(void)
2161 {
2162  return (RD_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL));
2163 }
2164 
2165 static INLINE void clk_systick_set(uint32_t val)
2166 {
2167  WR_WORD(GLOBAL_REG_SYSTICK_CLK_CTRL, val);
2168 }
2169 
2170 static INLINE void clk_reset_ipmac_clk(void)
2171 {
2172  uint32_t reg = RD_WORD(GLOBAL_REG_RESET_CTRL_2);
2173 
2174  reg &= ~(GLOBAL_REG_RESET_CTRL_2_CTL_RESET_2_D1_BLE_IPM_REG|GLOBAL_REG_RESET_CTRL_2_CTL_RESET_2_D1_BLE_IPMAC_REG);
2175  WR_WORD(GLOBAL_REG_RESET_CTRL_2, reg);
2176  reg |= GLOBAL_REG_RESET_CTRL_2_CTL_RESET_2_D1_BLE_IPM_REG|GLOBAL_REG_RESET_CTRL_2_CTL_RESET_2_D1_BLE_IPMAC_REG;
2177  WR_WORD(GLOBAL_REG_RESET_CTRL_2, reg);
2178 }
2179 
2180 static INLINE void clk_reset_adc(void)
2181 {
2182  uint32_t val;
2183  val = RD_WORD(GLOBAL_REG_RESET_CTRL_1);
2184  val &= ~GLOBAL_REG_RESET_CTRL_1_CTL_RESET_1_D0_SADC_RSTN_REG;
2185  WR_WORD(GLOBAL_REG_RESET_CTRL_1, val);
2186  val |= GLOBAL_REG_RESET_CTRL_1_CTL_RESET_1_D0_SADC_RSTN_REG;
2187  WR_WORD(GLOBAL_REG_RESET_CTRL_1, val);
2188 }
2189 
2190 static INLINE void clk_spiflash_en(int en)
2191 {
2192  uint32_t reg = RD_WORD(GLOBAL_REG_CLKD0_ENABLE_1);
2193 
2194  if (en) {
2195  reg |= GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SSI_MAS0_CLK;
2196  } else {
2197  reg &= ~(GLOBAL_REG_CLKD0_ENABLE_1_CTL_CLKD0_ENABLE_1_SSI_MAS0_CLK);
2198  }
2199  WR_WORD(GLOBAL_REG_CLKD0_ENABLE_1, reg);
2200 }
2201 
2202 static INLINE void clk_osc_xo_intr_clk_en(void)
2203 {
2204  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, (RD_WORD(GLOBAL_REG_CLK_ENABLE_1)|GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_OSC_XO_INTR_CLK));
2205 }
2206 
2207 static INLINE void clk_osc_xo_intr_clk_dis(void)
2208 {
2209  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, (RD_WORD(GLOBAL_REG_CLK_ENABLE_1)&~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_OSC_XO_INTR_CLK));
2210 }
2211 
2212 /*
2213  * Exported Functions
2214  ****************************************************************************************
2215  */
2216 
2224 void hal_clk_calib_xo(void);
2225 
2234 uint32_t hal_clk_root_get(void);
2235 
2236 
2246 int hal_clk_cpu_set(uint32_t cpu_clk);
2247 
2256 uint32_t hal_clk_cpu_get(void);
2257 
2267 int hal_clk_d0_mux(int mux);
2268 
2277 uint32_t hal_clk_d0_get(void);
2278 
2288 int hal_clk_d1_mux(int mux);
2289 
2298 uint32_t hal_clk_d1_get(void);
2299 
2309 int hal_clk_d2_mux(int mux);
2310 
2319 uint32_t hal_clk_d2_get(void);
2320 
2330 int hal_clk_tmr_mux(int tmr_id, int mux);
2331 
2340 uint32_t hal_clk_tmr_get(int tmr_id);
2341 
2351 int hal_clk_sadc_mux(int mux);
2352 
2361 uint32_t hal_clk_sadc_get(void);
2362 
2372 int hal_clk_smem_mux(int mux);
2373 
2383 int hal_clk_qspi_mux(int mux);
2384 
2394 void hal_clk_audio_sdm_mux(int mux);
2395 
2404 uint32_t hal_clk_qspi_get(void);
2405 
2415 int hal_clk_efuse_mux(int mux);
2416 
2426 void hal_clk_si2s_set(int ext_clk);
2427 
2437 void hal_clk_mi2s_set(uint32_t bit_clk);
2438 
2450 void hal_clk_audio_output(int mux);
2451 
2461 void hal_clk_efuse_en(int en);
2462 
2473 void hal_clk_uart_en(int id, int on);
2474 
2485 void hal_clk_i2c_en(int id, int on);
2486 
2496 void hal_clk_pwm_en(int on);
2497 
2507 void hal_clk_wdt_en(int on);
2508 
2518 void hal_clk_kb_en(int on);
2519 
2529 void hal_clk_ecc_en(int on);
2530 
2540 void hal_clk_hash_en(int on);
2541 
2551 void hal_clk_aes_en(int on);
2552 
2562 void hal_clk_counter_en(int on);
2563 
2573 void hal_clk_audio_en(int en);
2574 
2584 void hal_clk_audio_enc_en(int en);
2585 
2595 void hal_clk_audio_dec_en(int en);
2596 
2606 void hal_clk_audio_resample_en(int en);
2607 
2617 void hal_clk_sadc_en(int on);
2618 
2629 void hal_clk_i2s_en(int id, int on);
2630 
2640 void hal_clk_quaddec_en(int on);
2641 
2651 void hal_clk_dma_en(int on);
2652 
2662 void hal_clk_ble_en(int on);
2663 
2674 void hal_clk_gpio_intr(int port, int on);
2675 
2685 void hal_clk_mspi_en(int on);
2686 
2697 void hal_clk_sspi_en(int id, int on);
2698 
2708 void hal_clk_sm_en(int on);
2709 
2720 void hal_clk_tmr_en(int tim_id, int en);
2721 void hal_clk_cap_en(int tmr_id, int en);
2722 void hal_clk_emit_en(int tmr_id, int en);
2723 void hal_clk_aon_tmr_intr(int en);
2724 
2734 void hal_clk_32k(int clk_src);
2735 
2744 int hal_clk_32k_ready(void);
2745 
2754 uint32_t hal_clk_32k_get(void);
2755 
2766 void hal_clk_calib_32k(int cycles);
2767 
2768 
2778 int hal_clk_systick_mux(int mux);
2779 
2788 uint32_t hal_clk_systick_get(void);
2789 
2799 void hal_clk_systick_en(int en);
2800 
2801 
2802 
2803 
2805 
2806 #endif // HAL_CLK_H
hal_clk_32k_get
uint32_t hal_clk_32k_get(void)
Get slow clock (low power clock) rate.
CLK_EFUSE_DIV4
Divided by 4 of XO/32MRC.
Definition: hal_clk.h:84
hal_clk_i2c_en
void hal_clk_i2c_en(int id, int on)
Enable or disable I2c clock.
hal_clk_sm_en
void hal_clk_sm_en(int on)
Enable or disable share memory clock.
hal_clk_audio_en
void hal_clk_audio_en(int en)
Enable or disable shared audio clock.
hal_clk_root_get
uint32_t hal_clk_root_get(void)
Get Root clock.
hal_clk_counter_en
void hal_clk_counter_en(int on)
Enable or disable counter clock.
CLK_QSPI_DIV8
Divided by 8 of XO/32MRC.
Definition: hal_clk.h:110
hal_clk_systick_en
void hal_clk_systick_en(int en)
Enable or disable Inplay&#39;s systick clock.
CLK_D0_DIV1
Divided by 1 of 32MXO/32MRC. This is default.
Definition: hal_clk.h:36
hal_clk_smem_mux
int hal_clk_smem_mux(int mux)
Set Shared memory clock.
hal_clk_tmr_en
void hal_clk_tmr_en(int tim_id, int en)
Enable or disable Timer clock.
hal_clk_audio_dec_en
void hal_clk_audio_dec_en(int en)
Enable or disable audio decoder related clock.
hal_clk_gpio_intr
void hal_clk_gpio_intr(int port, int on)
Enable or disable GPIO interrupt controller clock.
CLK_TIM_DIV2
Divided by 2 of XO/32MRC.
Definition: hal_clk.h:68
hal_clk_wdt_en
void hal_clk_wdt_en(int on)
Enable or disable Watch Dog Timer clock.
hal_clk_efuse_mux
int hal_clk_efuse_mux(int mux)
Set Efuse clock.
hal_clk_d0_get
uint32_t hal_clk_d0_get(void)
Get D0 domanin clock.
hal_clk_cpu_get
uint32_t hal_clk_cpu_get(void)
Get CPU clock.
hal_clk_calib_xo
void hal_clk_calib_xo(void)
Calibrate XO.
hal_clk_kb_en
void hal_clk_kb_en(int on)
Enable or disable keyboard clock.
CLK_D2_DIV2
Divided by 2 of XO/32MRC. This is default.
Definition: hal_clk.h:56
hal_clk_audio_sdm_mux
void hal_clk_audio_sdm_mux(int mux)
Audio sigma delta modulator clock source mux.
CLK_QSPI_DIV2
Divided by 2 of XO/32MRC. This is default.
Definition: hal_clk.h:106
clk_sdm_mux
clk_sdm_mux
Audio speaker and SD clock mux.
Definition: hal_clk.h:72
clk_error
clk_error
Error return code.
Definition: hal_clk.h:125
CLK_QSPI_DIV1
Divided by 1 of XO/32MRC.
Definition: hal_clk.h:104
hal_clk_pwm_en
void hal_clk_pwm_en(int on)
Enable or disable PWM clock.
clk_smem_div
clk_smem_div
share memory clock divider
Definition: hal_clk.h:90
hal_clk_mi2s_set
void hal_clk_mi2s_set(uint32_t bit_clk)
Set Master I2S bit clock.
hal_clk_tmr_mux
int hal_clk_tmr_mux(int tmr_id, int mux)
Set Timer clock.
CLK_D1_DIV2
Divided by 2 of XOX2/XO/32MRC. This is default.
Definition: hal_clk.h:44
hal_clk_quaddec_en
void hal_clk_quaddec_en(int on)
Enable or disable QD clock.
tmr_id
tmr_id
Timer Id.
Definition: hal_timer.h:46
hal_clk_sadc_mux
int hal_clk_sadc_mux(int mux)
Set Sensor ADC clock.
clk_systick_div
clk_systick_div
systick clock divider
Definition: hal_clk.h:114
hal_clk_sadc_en
void hal_clk_sadc_en(int on)
Enable or disable sensor ADC clock.
CLK_D1_DIV8
Divided by 8 of XOX2/XO/32MRC.
Definition: hal_clk.h:48
hal_clk_systick_get
uint32_t hal_clk_systick_get(void)
Get Inplay systick clock.
CLK_I2S_MSTR_SCLK
I2S master clock generated from integer divider.
Definition: hal_clk.h:74
CLK_D0_DIV2
Divided by 2 of 32MXO/32MRC.
Definition: hal_clk.h:38
CLK_SMEM_DIV1
Divided by 1 of XO/32MRC.
Definition: hal_clk.h:92
hal_clk_ecc_en
void hal_clk_ecc_en(int on)
Enable or disable ECC clock.
CLK_SYSTICK_DIV16
Divided by 16 of XO/32MRC.
Definition: hal_clk.h:120
hal_clk_dma_en
void hal_clk_dma_en(int on)
Enable or disable DMA clock.
CLK_QSPI_DIV4
Divided by 4 of XO/32MRC.
Definition: hal_clk.h:108
hal_clk_d2_mux
int hal_clk_d2_mux(int mux)
Set D2 domain clock.
hal_clk_sspi_en
void hal_clk_sspi_en(int id, int on)
Enable or disable slave SPI clock.
hal_clk_calib_32k
void hal_clk_calib_32k(int cycles)
Calibrate Low Power Clock (RC/RTC) timer.
hal_clk_aes_en
void hal_clk_aes_en(int on)
Enable or disable AES clock.
hal_clk_tmr_get
uint32_t hal_clk_tmr_get(int tmr_id)
Get Timer clock.
CLK_TIM_DIV8
Divided by 8 of XO/32MRC.
Definition: hal_clk.h:66
CLK_D1_DIV4
Divided by 4 of XOX2/XO/32MRC.
Definition: hal_clk.h:46
hal_clk_cpu_set
int hal_clk_cpu_set(uint32_t cpu_clk)
Set CPU clock.
CLK_EFUSE_DIV8
Divided by 8 of XO/32MRC. This is default.
Definition: hal_clk.h:86
CLK_SMEM_DIV2
Divided by 2 of XO/32MRC. This is default.
Definition: hal_clk.h:94
CLK_TIM_DIV4
Divided by 4 of XO/32MRC.
Definition: hal_clk.h:64
hal_clk_qspi_get
uint32_t hal_clk_qspi_get(void)
Get QSPI clock.
CLK_ERR_NO_ERROR
No error.
Definition: hal_clk.h:127
hal_clk_uart_en
void hal_clk_uart_en(int id, int on)
Enable or disable Uart clock.
hal_clk_mspi_en
void hal_clk_mspi_en(int on)
Enable or disable master SPI clock.
hal_clk_qspi_mux
int hal_clk_qspi_mux(int mux)
Set QSPI speed clock.
hal_clk_d0_mux
int hal_clk_d0_mux(int mux)
Set D0 domain clock.
CLK_I2S_SLV_SCLK_PAD
I2S slave clock from PAD.
Definition: hal_clk.h:76
CLK_D2_DIV1
Divided by 1 of XO/32MRC.
Definition: hal_clk.h:54
hal_clk_32k_ready
int hal_clk_32k_ready(void)
Check if RTC is ready.
CLK_SMEM_DIV4
Divided by 4 of XO/32MRC.
Definition: hal_clk.h:96
CLK_ERR_INVALID_PARAM
Invalid input paramters.
Definition: hal_clk.h:129
CLK_D2_DIV4
Divided by 4 of XO/32MRC.
Definition: hal_clk.h:58
hal_clk_i2s_en
void hal_clk_i2s_en(int id, int on)
Enable or disable I2S clock.
hal_clk_audio_enc_en
void hal_clk_audio_enc_en(int en)
Enable or disable audio encoder related clock.
CLK_SMEM_DIV8
Divided by 8 of XO/32MRC.
Definition: hal_clk.h:98
hal_clk_d1_mux
int hal_clk_d1_mux(int mux)
Set D1 domain clock.
hal_clk_hash_en
void hal_clk_hash_en(int on)
Enable or disable hash clock.
CLK_SYSTICK_DIV4
Divided by 4 of XO/32MRC. This is default.
Definition: hal_clk.h:116
hal_clk_efuse_en
void hal_clk_efuse_en(int en)
Enable or disable Efuse clock.
hal_clk_audio_resample_en
void hal_clk_audio_resample_en(int en)
Enable or disable audio reampling related clock.
clk_d0_div
clk_d0_div
Clock D0 domain divider.
Definition: hal_clk.h:34
hal_clk_si2s_set
void hal_clk_si2s_set(int ext_clk)
Set Slave I2S clock source.
CLK_PDM
PDM clock.
Definition: hal_clk.h:78
hal_clk_sadc_get
uint32_t hal_clk_sadc_get(void)
Get SADC clock.
hal_clk_d2_get
uint32_t hal_clk_d2_get(void)
Get D2 domanin clock.
hal_clk_32k
void hal_clk_32k(int clk_src)
Select 32k clock source.
clk_d1_div
clk_d1_div
Clock D1 domain divider.
Definition: hal_clk.h:42
clk_efuse_div
clk_efuse_div
Efuse clock divider.
Definition: hal_clk.h:82
clk_qspi_div
clk_qspi_div
QSPI serial clock divider.
Definition: hal_clk.h:102
clk_d2_div
clk_d2_div
Clock D2 domain divider.
Definition: hal_clk.h:52
hal_clk_systick_mux
int hal_clk_systick_mux(int mux)
Set Inplay&#39;s Systick clock.
CLK_SYSTICK_DIV8
Divided by 8 of XO/32MRC.
Definition: hal_clk.h:118
hal_clk_ble_en
void hal_clk_ble_en(int on)
Enable or disable BLE clock.
hal_clk_d1_get
uint32_t hal_clk_d1_get(void)
Get D1 domanin clock.
clk_tim_div
clk_tim_div
Timer clock 1 divider.
Definition: hal_clk.h:62
hal_clk_audio_output
void hal_clk_audio_output(int mux)
Set audio output (Speaker/Sigma Delta) clock mux.