InPlay API
hal_wdt.h
1 
13 #ifndef HAL_WDT_H
14 #define HAL_WDT_H
15 
25 #include "in_mmap.h"
26 
27 /*
28  * Defines Regular WDT (no sleep)
29  ****************************************************************************************
30  */
31 
32 #define WDT_REG_CR_OFS 0x00000000UL
33 #define WDT_REG_TOR_OFS 0x00000004UL
34 #define WDT_REG_CVR_OFS 0x00000008UL
35 #define WDT_REG_CRR_OFS 0x0000000CUL
36 #define WDT_REG_ISR_OFS 0x00000010UL
37 #define WDT_REG_EOI_OFS 0x00000014UL
38 
39 #define WDT_CR_WDT_EN 0x00000001UL
40 #define WDT_CR_RMOD 0x00000002UL
41 
42 #define WDT_TORR_TOP 0x0000000FUL
43 #define WDT_TORR_TOP_INIT 0x000000F0UL
44 
45 #define WDT_INT_PD1_TMO 0x1
46 #define WDT_INT_PD1_SYS_RST 0x2
47 #define WDT_INT_AON 0x4
48 
49 #define WDT_RST_OUTPUT_PIN_POL_HIGH 1
50 #define WDT_RST_OUTPUT_PIN_POL_LOW 0
51 
52 /*
53  * Enum
54  ****************************************************************************************
55  */
56 
57 enum wdt_error {
58  WDT_ERR_OK = 0,
59  WDT_ERR_INVALID_PARAM = -1,
60 } ;
61 
62 typedef enum wdt_reset_mode {
63  WDT_RESET_NONE = 0,
64  WDT_RESET_ARM,
65  WDT_RESET_CHIP
66 } wdt_reset_mode_t;
67 
68 typedef enum wdt_reset_output_pin_e {
69  WDT_RESET_O_PIN_0_0 = 0,
70  WDT_RESET_O_PIN_0_4,
71  WDT_RESET_O_PIN_0_8,
72  WDT_RESET_O_PIN_1_2,
73  WDT_RESET_O_PIN_1_6,
74  WDT_RESET_O_PIN_3_5,
75  WDT_RESET_O_PIN_4_1,
76  WDT_RESET_O_PIN_NONE,
77 } wdt_rst_o_pin_t;
78 
79 typedef struct wdt_cfg_param_s
80 {
81  uint32_t timeout_ms;
82  wdt_reset_mode_t reset_mode;
83  wdt_rst_o_pin_t rst_out_pin;
84  uint8_t rst_out_pin_pol;
85  uint8_t wakeup_en;
86 }wdt_cfg_param_t;
87 
88 /*
89  * Inline AON WDT Functions
90  ****************************************************************************************
91  */
92 
93 static INLINE void aon_wdt_clk_src(int rtc)
94 {
95  uint32_t reg = RD_WORD(AON_REG_AON_MISC_CTRL);
96 
97  if (rtc) {
98  reg |= AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK;
99  reg |= AON_REG_AON_MISC_CTRL_CTL_WDT_RST_SWITCH_RC_CLK;
100  } else {
101  reg &= ~AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK;
102  }
103 
104  WR_WORD(AON_REG_AON_MISC_CTRL, reg);
105 }
106 
107 static INLINE void aon_wdt_wup(int en)
108 {
109  uint32_t reg = RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL);
110 
111  if (en) {
112  reg |= AON_REG_AON_TIMER_WAKE_UP_SEL_CTL_AON_TIMER_WDT_WAKEUP_EN;
113  } else {
114  reg &= ~AON_REG_AON_TIMER_WAKE_UP_SEL_CTL_AON_TIMER_WDT_WAKEUP_EN;
115  }
116 
117  WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, reg);
118 }
119 
120 static INLINE void aon_wdt_clk_en(int en)
121 {
122  uint32_t reg = RD_WORD(AON_REG_AON_TIMER_CLK_CTRL);
123  if (en)
124  reg |= AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_CLK_EN;
125  else
126  reg &= ~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_CLK_EN;
127 
128  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, reg);
129 }
130 
131 
132 static INLINE void aon_wdt_reload_en(int en)
133 {
134  uint32_t reg = RD_WORD(AON_REG_AON_TIMER_CLK_CTRL);
135  if (en)
136  reg |= AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_AUTO_RELOAD_EN;
137  else
138  reg &= ~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_AUTO_RELOAD_EN;
139 
140  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, reg);
141 }
142 
143 static INLINE void aon_wdt_reset_pd0(uint8_t clk_cycles, int rst_out_pol)
144 {
145  uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD0;
146  reg |= ( rst_out_pol > 0) ? AON_REG_AON_TIMER_WDT_CTRL_CTL_WDT_RST_OUTPUT_POLARITY : 0;
147  reg |= ((clk_cycles & AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD0_RESET_DLY_MASK) << AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD0_RESET_DLY_SHIFT);
148  WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
149 }
150 
151 static INLINE void aon_wdt_reset_pd1(uint8_t clk_cycles, int rst_out_pol)
152 {
153  uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD1;
154  reg |= ( rst_out_pol > 0) ? AON_REG_AON_TIMER_WDT_CTRL_CTL_WDT_RST_OUTPUT_POLARITY : 0;
155  reg |= ((clk_cycles & AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD1_RESET_DLY_MASK) << AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD1_RESET_DLY_SHIFT);
156  WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
157 }
158 
159 static INLINE void aon_wdt_reset_chip_disable(void)
160 {
161  uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_DEFAULT;
162  reg &= (~(AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD1));
163  reg &= (~(AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD0));
164  WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
165 }
166 
167 static INLINE void aon_wdt_int_clk(int enable)
168 {
169  uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
170 
171  if (enable) {
172  reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
173  } else {
174  reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
175  }
176 
177  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
178 }
179 
180 static INLINE void aon_wdt(int en)
181 {
182  uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
183  if (en)
184  reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN;
185  else {
186  reg &= ~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN;
187  reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_CTRL_SYNC_32K_RST_N;
188  }
189  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
190 
191  if (en) {
192  while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN));
193  } else {
194  while ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN));
195  }
196 }
197 
198 static INLINE void aon_wdt_en(void)
199 {
200  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN));
201  int retry = 0;
202  while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN)) {
203  retry += 1;
204  if (retry > 20) {
205  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN));
206  retry = 0;
207  }
208  }
209 }
210 
211 static INLINE void aon_wdt_dis(void)
212 {
213  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)&~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_CTRL_SYNC_32K_RST_N));
214  int retry = 0;
215  while ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN)) {
216  retry += 1;
217  if (retry > 0) {
218  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)&~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN)));
219  retry = 0;
220  }
221  }
222 }
223 
224 static INLINE void aon_wdt_irq_clear(void)
225 {
226  uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
227  reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_IRQ_CLR;
228  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
229 
230  while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_IRQ_CLR));
231 }
232 
233 static INLINE void aon_wdt_touch(void)
234 {
235  uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
236  reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_TOUCH;
237  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
238 
239  while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_TOUCH));
240 }
241 
242 static INLINE void aon_wdt_init_val(uint32_t val)
243 {
244  WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_INIT_VAL, val);
245  while (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_INIT_VAL_STS) != val);
246 }
247 
248 static INLINE uint32_t aon_wdt_read_tick(void)
249 {
250  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_WDT_TAKE_SNAPSHOT);
251  return (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_SNAPSHOT_VAL));
252 }
253 
254 static INLINE uint32_t aon_wdt_int_status(void)
255 {
256  return (RD_WORD(GLOBAL2_REG_WDT_INTR_STATUS));
257 }
258 
259 static INLINE uint32_t aon_wdt_int_mask_status(void)
260 {
261  return (RD_WORD(GLOBAL2_REG_WDT_INTR_MASK_STATUS));
262 }
263 
264 static INLINE void aon_wdt_int_clear(uint32_t status)
265 {
266  WR_WORD(GLOBAL2_REG_WDT_INTR_CLEAR, status);
267 }
268 
269 static INLINE void aon_wdt_int_mask(uint32_t mask)
270 {
271  WR_WORD(GLOBAL2_REG_WDT_INTR_MASK_SET, mask);
272 }
273 
274 static INLINE void aon_wdt_int_mask_clear(uint32_t mask)
275 {
276  WR_WORD(GLOBAL2_REG_WDT_INTR_MASK_CLEAR, mask);
277 }
278 
279 /*
280  * Enumeratios
281  ****************************************************************************************
282  */
283 
284 /*
285  * Functions
286  ****************************************************************************************
287  */
288 
300 int hal_aon_wdt_start(wdt_cfg_param_t *cfg, void (*callback)(void *arg), void *arg);
301 
302 
311 void hal_aon_wdt_touch(void);
312 
313 void hal_aon_wdt_stop(void);
314 
316 
317 #endif // HAL_WDT_H
void hal_aon_wdt_touch(void)
Reload the watch dog timer counter.
int hal_aon_wdt_start(wdt_cfg_param_t *cfg, void(*callback)(void *arg), void *arg)
Enable watch dog timer.