32 #define WDT_REG_CR_OFS 0x00000000UL 33 #define WDT_REG_TOR_OFS 0x00000004UL 34 #define WDT_REG_CVR_OFS 0x00000008UL 35 #define WDT_REG_CRR_OFS 0x0000000CUL 36 #define WDT_REG_ISR_OFS 0x00000010UL 37 #define WDT_REG_EOI_OFS 0x00000014UL 39 #define WDT_CR_WDT_EN 0x00000001UL 40 #define WDT_CR_RMOD 0x00000002UL 42 #define WDT_TORR_TOP 0x0000000FUL 43 #define WDT_TORR_TOP_INIT 0x000000F0UL 45 #define WDT_INT_PD1_TMO 0x1 46 #define WDT_INT_PD1_SYS_RST 0x2 47 #define WDT_INT_AON 0x4 49 #define WDT_RST_OUTPUT_PIN_POL_HIGH 1 50 #define WDT_RST_OUTPUT_PIN_POL_LOW 0 59 WDT_ERR_INVALID_PARAM = -1,
62 typedef enum wdt_reset_mode {
68 typedef enum wdt_reset_output_pin_e {
69 WDT_RESET_O_PIN_0_0 = 0,
79 typedef struct wdt_cfg_param_s
82 wdt_reset_mode_t reset_mode;
83 wdt_rst_o_pin_t rst_out_pin;
84 uint8_t rst_out_pin_pol;
93 static INLINE
void aon_wdt_clk_src(
int rtc)
95 uint32_t reg = RD_WORD(AON_REG_AON_MISC_CTRL);
98 reg |= AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK;
99 reg |= AON_REG_AON_MISC_CTRL_CTL_WDT_RST_SWITCH_RC_CLK;
101 reg &= ~AON_REG_AON_MISC_CTRL_CTL_SEL_TIMER_WDT_32K_CLK;
104 WR_WORD(AON_REG_AON_MISC_CTRL, reg);
107 static INLINE
void aon_wdt_wup(
int en)
109 uint32_t reg = RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL);
112 reg |= AON_REG_AON_TIMER_WAKE_UP_SEL_CTL_AON_TIMER_WDT_WAKEUP_EN;
114 reg &= ~AON_REG_AON_TIMER_WAKE_UP_SEL_CTL_AON_TIMER_WDT_WAKEUP_EN;
117 WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, reg);
120 static INLINE
void aon_wdt_clk_en(
int en)
122 uint32_t reg = RD_WORD(AON_REG_AON_TIMER_CLK_CTRL);
124 reg |= AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_CLK_EN;
126 reg &= ~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_CLK_EN;
128 WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, reg);
132 static INLINE
void aon_wdt_reload_en(
int en)
134 uint32_t reg = RD_WORD(AON_REG_AON_TIMER_CLK_CTRL);
136 reg |= AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_AUTO_RELOAD_EN;
138 reg &= ~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER_WDT_AUTO_RELOAD_EN;
140 WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, reg);
143 static INLINE
void aon_wdt_reset_pd0(uint8_t clk_cycles,
int rst_out_pol)
145 uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD0;
146 reg |= ( rst_out_pol > 0) ? AON_REG_AON_TIMER_WDT_CTRL_CTL_WDT_RST_OUTPUT_POLARITY : 0;
147 reg |= ((clk_cycles & AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD0_RESET_DLY_MASK) << AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD0_RESET_DLY_SHIFT);
148 WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
151 static INLINE
void aon_wdt_reset_pd1(uint8_t clk_cycles,
int rst_out_pol)
153 uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD1;
154 reg |= ( rst_out_pol > 0) ? AON_REG_AON_TIMER_WDT_CTRL_CTL_WDT_RST_OUTPUT_POLARITY : 0;
155 reg |= ((clk_cycles & AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD1_RESET_DLY_MASK) << AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_PD1_RESET_DLY_SHIFT);
156 WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
159 static INLINE
void aon_wdt_reset_chip_disable(
void)
161 uint32_t reg = AON_REG_AON_TIMER_WDT_CTRL_DEFAULT;
162 reg &= (~(AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD1));
163 reg &= (~(AON_REG_AON_TIMER_WDT_CTRL_CTL_AON_TIMER_WDT_RESET_PD0));
164 WR_WORD(AON_REG_AON_TIMER_WDT_CTRL, reg);
167 static INLINE
void aon_wdt_int_clk(
int enable)
169 uint32_t reg = RD_WORD(GLOBAL_REG_CLK_ENABLE_1);
172 reg |= GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
174 reg &= ~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_WDT_INTR_CLK;
177 WR_WORD(GLOBAL_REG_CLK_ENABLE_1, reg);
180 static INLINE
void aon_wdt(
int en)
182 uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
184 reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN;
186 reg &= ~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN;
187 reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_CTRL_SYNC_32K_RST_N;
189 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
192 while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN));
194 while ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN));
198 static INLINE
void aon_wdt_en(
void)
200 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN));
202 while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN)) {
205 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN));
211 static INLINE
void aon_wdt_dis(
void)
213 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)&~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN)|GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_CTRL_SYNC_32K_RST_N));
215 while ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_EN)) {
218 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, ((RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL)&~GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_EN)));
224 static INLINE
void aon_wdt_irq_clear(
void)
226 uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
227 reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_IRQ_CLR;
228 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
230 while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_IRQ_CLR));
233 static INLINE
void aon_wdt_touch(
void)
235 uint32_t reg = RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL);
236 reg |= GLOBAL2_REG_AON_TIMER_WDT_CTL_CTL_AON_TIMER_WDT_TOUCH;
237 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_CTL, reg);
239 while (!(RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_STS) & GLOBAL2_REG_AON_TIMER_WDT_STS_STS_AON_TIMER_WDT_TOUCH));
242 static INLINE
void aon_wdt_init_val(uint32_t val)
244 WR_WORD(GLOBAL2_REG_AON_TIMER_WDT_INIT_VAL, val);
245 while (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_INIT_VAL_STS) != val);
248 static INLINE uint32_t aon_wdt_read_tick(
void)
250 WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_WDT_TAKE_SNAPSHOT);
251 return (RD_WORD(GLOBAL2_REG_AON_TIMER_WDT_SNAPSHOT_VAL));
254 static INLINE uint32_t aon_wdt_int_status(
void)
256 return (RD_WORD(GLOBAL2_REG_WDT_INTR_STATUS));
259 static INLINE uint32_t aon_wdt_int_mask_status(
void)
261 return (RD_WORD(GLOBAL2_REG_WDT_INTR_MASK_STATUS));
264 static INLINE
void aon_wdt_int_clear(uint32_t status)
266 WR_WORD(GLOBAL2_REG_WDT_INTR_CLEAR, status);
269 static INLINE
void aon_wdt_int_mask(uint32_t mask)
271 WR_WORD(GLOBAL2_REG_WDT_INTR_MASK_SET, mask);
274 static INLINE
void aon_wdt_int_mask_clear(uint32_t mask)
276 WR_WORD(GLOBAL2_REG_WDT_INTR_MASK_CLEAR, mask);
300 int hal_aon_wdt_start(wdt_cfg_param_t *cfg,
void (*callback)(
void *arg),
void *arg);
313 void hal_aon_wdt_stop(
void);
void hal_aon_wdt_touch(void)
Reload the watch dog timer counter.
int hal_aon_wdt_start(wdt_cfg_param_t *cfg, void(*callback)(void *arg), void *arg)
Enable watch dog timer.