InPlay API
hal_timer.h
1 
13 #ifndef HAL_TIMER_H
14 #define HAL_TIMER_H
15 
25 #include "in_mmap.h"
26 #include "in_compile.h"
27 #include "./hal/hal_clk.h"
28 
29 /*
30  * Defines Regular Timer (no sleep)
31  ****************************************************************************************
32  */
33 
34 #define TMR_SMEM_EMIT_EMPTY 0x1
35 #define TMR_SMEM_CAP_FULL 0x2
36 #define TMR_SMEM_EMIT_FIFO_UNDERFLOW 0x4
37 #define TMR_SMEM_EMIT_FIFO_OVERFLOW 0x8
38 #define TMR_SMEM_EMIT_REG_FIFO_UNDERFLOW 0x10
39 #define TMR_SMEM_EMIT_REG_FIFO_OVERFLOW 0x20
40 #define TMR_SMEM_CAP_FIFO_UNDERFLOW 0x40
41 #define TMR_SMEM_CAP_FIFO_OVERFLOW 0x80
42 #define TMR_SMEM_CAP_REG_FIFO_UNDERFLOW 0x100
43 #define TMR_SMEM_CAP_REG_FIFO_OVERFLOW 0x200
44 
46 enum tmr_id {
47  TMR0_ID,
48  TMR1_ID,
49  TMR2_ID,
50  TMR3_ID,
51  TMR4_ID,
52  TMR5_ID,
53  TMR6_ID, //adv timer
54  TMR7_ID,
55  TMR8_ID,
56  TMR9_ID,
57  TMR_ID_MAX,
58 };
59 
61 enum cap_id {
62  CAP0_ID,
63  CAP1_ID,
64  CAP2_ID,
65  CAP3_ID,
66  CAP_ID_MAX,
67 };
68 
70 enum emit_id {
71  EMIT0_ID,
72  EMIT1_ID,
73  EMIT2_ID,
74  EMIT3_ID,
75  EMIT4_ID,
76  EMIT5_ID,
77  EMIT6_ID,
78  EMIT7_ID,
79  EMIT8_ID,
80  EMIT9_ID,
81  EMIT_ID_MAX,
82 };
83 
84 typedef struct tmr_emit_option_s{
85  uint8_t auto_clr; //Clear the emit signal automatically
86  uint8_t touch_clr; //Clear the emit signal by write to touch register
87  uint8_t sig_default;
88  uint8_t sig_toggle;
89  uint8_t toggle_default;
90  uint8_t toggle_pol;
91 } tmr_emit_option_t;
92 
93 /*
94  * Defines Timer
95  ****************************************************************************************
96  */
97 
98 
99 /*
100  * Defines Slow Timer (can sleep)
101  ****************************************************************************************
102  */
103 
104 #define SLP_TMR_NB 4
105 #define SLP_TMR_MAX_64 0xFFFFFFFFFFFFFFFF
106 #define SLP_TMR_MAX_32 0xFFFFFFFF
107 
108 enum aon_tmr_id {
109  AON_TMR0_ID,
110  AON_TMR1_ID,
111  AON_TMR2_ID,
112  AON_TMR3_ID,
113  AON_TMR_MAX,
114 };
115 
116 enum aon_tmr_sts {
117  AON_TMR_STS_EN = 0x1,
118  AON_TMR_STS_TOUCH = 0x2,
119  AON_TMR_STS_IRQ_CLR = 0x4,
120  AON_TMR_STS_MANU_MODE = 0x8,
121  AON_TMR_STS_MANU_TICK = 0x10,
122 };
123 
124 enum aon_cap_id {
125  AON_CAP0_ID,
126  AON_CAP1_ID,
127  AON_CAP_ID_MAX,
128 };
129 
130 enum aon_emit_id {
131  AON_EMIT0_ID,
132  AON_EMIT1_ID,
133  AON_EMIT_ID_MAX,
134 };
135 
136 enum aon_int_status_bit {
137  AON_TMR0_INT_TMO,
138  AON_TMR1_INT_TMO,
139  AON_TMR2_INT_TMO,
140  AON_TMR3_INT_TMO,
141  AON_TMR2_INT_CAP0,
142  AON_TMR2_INT_CAP1,
143  AON_TMR2_INT_EMIT0,
144  AON_TMR2_INT_EMIT1,
145 };
146 
147 
148 /*
149  * Defines Shared (sleep and non sleep) Error Code
150  ****************************************************************************************
151  */
153 enum tmr_err {
154  TMR_ERR_OK = 0,
155  TMR_ERR_INVALID_PARAM = -1,
156  TMR_ERR_IN_USE = -2,
157  TMR_ERR_BAD_STATE = -3,
158  TMR_ERR_INVALID_ID = -4,
159  TMR_ERR_NOT_READY = -5,
160  TMR_ERR_TIMEOUT = -6,
161 } ;
162 
163 /*
164  * Inline AON Functions
165  ****************************************************************************************
166  */
167 
168 static FORCEINLINE void aon_tmr_init_tick(uint32_t addr, uint32_t tick)
169 {
170  WR_WORD(addr, tick);
171 }
172 
173 static FORCEINLINE uint32_t aon_tmr_init_tick_sts(uint32_t addr)
174 {
175  return (RD_WORD(addr));
176 }
177 
178 static FORCEINLINE void aon_tmr0_init_tick(uint32_t tick)
179 {
180  WR_WORD(GLOBAL2_REG_AON_TIMER_0_INIT_VAL, tick);
181 }
182 
183 static FORCEINLINE uint32_t aon_tmr0_init_tick_sts(void)
184 {
185  return RD_WORD(GLOBAL2_REG_AON_TIMER_0_INIT_VAL_STS);
186 }
187 
188 static FORCEINLINE void aon_tmr1_init_tick(uint32_t tick)
189 {
190  WR_WORD(GLOBAL2_REG_AON_TIMER_1_INIT_VAL, tick);
191 }
192 
193 static FORCEINLINE uint32_t aon_tmr1_init_tick_sts(void)
194 {
195  return RD_WORD(GLOBAL2_REG_AON_TIMER_1_INIT_VAL_STS);
196 }
197 
198 static FORCEINLINE void aon_tmr2_init_tick(uint32_t tick)
199 {
200  WR_WORD(GLOBAL2_REG_AON_TIMER_2_INIT_VAL, tick);
201 }
202 
203 static FORCEINLINE uint32_t aon_tmr2_init_tick_sts(void)
204 {
205  return RD_WORD(GLOBAL2_REG_AON_TIMER_2_INIT_VAL_STS);
206 }
207 
208 static FORCEINLINE void aon_tmr3_init_tick(uint64_t tick)
209 {
210  WR_WORD(GLOBAL2_REG_AON_TIMER_3_INIT_VAL_LO, (uint32_t)tick);
211  WR_WORD(GLOBAL2_REG_AON_TIMER_3_INIT_VAL_HI, (uint32_t)(tick >> 32));
212 }
213 
214 static FORCEINLINE uint64_t aon_tmr3_init_tick_sts(void)
215 {
216  return (RD_WORD(GLOBAL2_REG_AON_TIMER_3_INIT_VAL_LO_STS) | ((uint64_t)RD_WORD(GLOBAL2_REG_AON_TIMER_3_INIT_VAL_HI_STS) << 32)) ;
217 }
218 
219 static FORCEINLINE void aon_tmr_snap_tick(int id)
220 {
221  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, (1 << 20 << id));
222  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
223 }
224 
225 static FORCEINLINE uint32_t aon_tmr_read_tick(uint32_t addr)
226 {
227  return RD_WORD(addr);
228 }
229 
230 static FORCEINLINE void aon_tmr0_snap_tick(void)
231 {
232  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_0_TAKE_SNAPSHOT);
233  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
234 }
235 
236 static FORCEINLINE uint32_t aon_tmr0_read_tick(int id)
237 {
238  return RD_WORD(GLOBAL2_REG_AON_TIMER_0_SNAPSHOT_VAL);
239 }
240 
241 static FORCEINLINE void aon_tmr1_snap_tick(void)
242 {
243  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_1_TAKE_SNAPSHOT);
244  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
245 }
246 
247 static FORCEINLINE uint32_t aon_tmr1_read_tick(int id)
248 {
249  return RD_WORD(GLOBAL2_REG_AON_TIMER_1_SNAPSHOT_VAL);
250 }
251 
252 static FORCEINLINE void aon_tmr2_snap_tick(void)
253 {
254  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_2_TAKE_SNAPSHOT);
255  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
256 }
257 
258 static FORCEINLINE uint32_t aon_tmr2_read_tick(int id)
259 {
260  return RD_WORD(GLOBAL2_REG_AON_TIMER_2_SNAPSHOT_VAL);
261 }
262 
263 static FORCEINLINE void aon_tmr3_snap_tick(void)
264 {
265  WR_WORD(GLOBAL2_REG_SNAPSHOT_CTRL, GLOBAL2_REG_SNAPSHOT_CTRL_CTL_AON_TIMER_3_TAKE_SNAPSHOT);
266  RD_WORD(GLOBAL2_REG_SNAPSHOT_CTRL);
267 }
268 
269 static FORCEINLINE uint64_t aon_tmr3_read_tick(void)
270 {
271  return (RD_WORD(GLOBAL2_REG_AON_TIMER_3_SNAPSHOT_VAL_LO)|((uint64_t)RD_WORD(GLOBAL2_REG_AON_TIMER_3_SNAPSHOT_VAL_HI) << 32));
272 }
273 
274 static FORCEINLINE void aon_tmr_clk_en(int id)
275 {
276  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|(1 << id)));
277 }
278 
279 static FORCEINLINE void aon_tmr_clk_dis(int id)
280 {
281  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~(1 << id)));
282 }
283 
284 static FORCEINLINE void aon_tmr0_clk_en(void)
285 {
286  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER0_CLK_EN));
287 }
288 
289 static FORCEINLINE void aon_tmr0_clk_dis(void)
290 {
291  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER0_CLK_EN));
292 }
293 
294 static FORCEINLINE void aon_tmr1_clk_en(void)
295 {
296  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER1_CLK_EN));
297 }
298 
299 static FORCEINLINE void aon_tmr1_clk_dis(void)
300 {
301  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER1_CLK_EN));
302 }
303 
304 static FORCEINLINE void aon_tmr2_clk_en(void)
305 {
306  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_CLK_EN));
307 }
308 
309 static FORCEINLINE void aon_tmr2_clk_dis(void)
310 {
311  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_CLK_EN));
312 }
313 
314 static FORCEINLINE void aon_tmr3_clk_en(void)
315 {
316  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER3_CLK_EN));
317 }
318 
319 static FORCEINLINE void aon_tmr3_clk_dis(void)
320 {
321  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER3_CLK_EN));
322 }
323 
324 static FORCEINLINE void aon_tmr_reload_en(int id)
325 {
326  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|(1 << 8 << id)));
327 }
328 
329 static FORCEINLINE void aon_tmr_reload_dis(int id)
330 {
331  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~(1 << 8 << id)));
332 }
333 
334 static FORCEINLINE void aon_tmr0_reload_en(void)
335 {
336  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER0_AUTO_RELOAD_EN));
337 }
338 
339 static FORCEINLINE void aon_tmr0_reload_dis(void)
340 {
341  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER0_AUTO_RELOAD_EN));
342 }
343 
344 static FORCEINLINE void aon_tmr1_reload_en(void)
345 {
346  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER1_AUTO_RELOAD_EN));
347 }
348 
349 static FORCEINLINE void aon_tmr1_reload_dis(void)
350 {
351  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER1_AUTO_RELOAD_EN));
352 }
353 
354 static FORCEINLINE void aon_tmr2_reload_en(void)
355 {
356  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_AUTO_RELOAD_EN));
357 }
358 
359 static FORCEINLINE void aon_tmr2_reload_dis(void)
360 {
361  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_AUTO_RELOAD_EN));
362 }
363 
364 static FORCEINLINE void aon_tmr3_reload_en(void)
365 {
366  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER3_AUTO_RELOAD_EN));
367 }
368 
369 static FORCEINLINE void aon_tmr3_reload_dis(void)
370 {
371  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER3_AUTO_RELOAD_EN));
372 }
373 
374 static FORCEINLINE void aon_tmr_en(uint32_t addr)
375 {
376  WR_WORD(addr, (RD_WORD(addr)|Bit0));
377 }
378 
379 static FORCEINLINE int aon_tmr_en_sts(uint32_t addr)
380 {
381  return (RD_WORD(addr) & Bit0);
382 }
383 
384 static FORCEINLINE void aon_tmr0_en(void)
385 {
386  WR_WORD(GLOBAL2_REG_AON_TIMER_0_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_0_CTL)|Bit0));
387 }
388 
389 static FORCEINLINE int aon_tmr0_en_sts(void)
390 {
391  return (RD_WORD(GLOBAL2_REG_AON_TIMER_0_STS) & Bit0);
392 }
393 
394 static FORCEINLINE void aon_tmr1_en(void)
395 {
396  WR_WORD(GLOBAL2_REG_AON_TIMER_1_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_1_CTL)|Bit0));
397 }
398 
399 static FORCEINLINE int aon_tmr1_en_sts(void)
400 {
401  return (RD_WORD(GLOBAL2_REG_AON_TIMER_1_STS) & Bit0);
402 }
403 
404 static FORCEINLINE void aon_tmr2_en(void)
405 {
406  WR_WORD(GLOBAL2_REG_AON_TIMER_2_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_2_CTL)|Bit0));
407 }
408 
409 static FORCEINLINE int aon_tmr2_en_sts(void)
410 {
411  return (RD_WORD(GLOBAL2_REG_AON_TIMER_2_STS) & Bit0);
412 }
413 
414 static FORCEINLINE void aon_tmr3_en(void)
415 {
416  WR_WORD(GLOBAL2_REG_AON_TIMER_3_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_3_CTL)|Bit0));
417 }
418 
419 static FORCEINLINE int aon_tmr3_en_sts(void)
420 {
421  return (RD_WORD(GLOBAL2_REG_AON_TIMER_3_STS) & Bit0);
422 }
423 
424 static FORCEINLINE void aon_tmr_dis(uint32_t addr)
425 {
426  WR_WORD(addr, (RD_WORD(addr)&~Bit0));
427 }
428 
429 static FORCEINLINE int aon_tmr_dis_sts(uint32_t addr)
430 {
431  return ((RD_WORD(addr) & Bit0) ? 0 : 1);
432 }
433 
434 static FORCEINLINE void aon_tmr0_dis(void)
435 {
436  WR_WORD(GLOBAL2_REG_AON_TIMER_0_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_0_CTL)&~Bit0));
437 }
438 
439 static FORCEINLINE int aon_tmr0_dis_sts(void)
440 {
441  return ((RD_WORD(GLOBAL2_REG_AON_TIMER_0_STS) & Bit0) ? 0 : 1);
442 }
443 
444 static FORCEINLINE void aon_tmr1_dis(void)
445 {
446  WR_WORD(GLOBAL2_REG_AON_TIMER_1_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_1_CTL)&~Bit0));
447 }
448 
449 static FORCEINLINE int aon_tmr1_dis_sts(void)
450 {
451  return ((RD_WORD(GLOBAL2_REG_AON_TIMER_1_STS) & Bit0) ? 0 : 1);
452 }
453 
454 static FORCEINLINE void aon_tmr2_dis(void)
455 {
456  WR_WORD(GLOBAL2_REG_AON_TIMER_2_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_2_CTL)&~Bit0));
457 }
458 
459 static FORCEINLINE int aon_tmr2_dis_sts(void)
460 {
461  return ((RD_WORD(GLOBAL2_REG_AON_TIMER_2_STS) & Bit0) ? 0 : 1);
462 }
463 
464 static FORCEINLINE void aon_tmr3_dis(void)
465 {
466  WR_WORD(GLOBAL2_REG_AON_TIMER_3_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_3_CTL)&~Bit0));
467 }
468 
469 static FORCEINLINE int aon_tmr3_dis_sts(void)
470 {
471  return ((RD_WORD(GLOBAL2_REG_AON_TIMER_3_STS) & Bit0) ? 0 : 1);
472 }
473 
474 static FORCEINLINE void aon_tmr_touch(uint32_t addr)
475 {
476  WR_WORD(addr, (RD_WORD(addr) | Bit1));
477 }
478 
479 static FORCEINLINE int aon_tmr_touch_sts(uint32_t addr)
480 {
481  return (RD_WORD(addr) & Bit1);
482 }
483 
484 static FORCEINLINE void aon_tmr0_touch(void)
485 {
486  WR_WORD(GLOBAL2_REG_AON_TIMER_0_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_0_CTL)|Bit1));
487 }
488 
489 static FORCEINLINE int aon_tmr0_touch_sts(void)
490 {
491  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_0_STS) & Bit1) >> 1) & 1);
492 }
493 
494 static FORCEINLINE void aon_tmr1_touch(int toggle)
495 {
496  WR_WORD(GLOBAL2_REG_AON_TIMER_1_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_1_CTL)|Bit1));
497 }
498 
499 static FORCEINLINE int aon_tmr1_touch_sts(void)
500 {
501  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_1_STS) & Bit1) >> 1) & 1);
502 }
503 
504 static FORCEINLINE void aon_tmr2_touch(int toggle)
505 {
506  WR_WORD(GLOBAL2_REG_AON_TIMER_2_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_2_CTL)|Bit1));
507 }
508 
509 static FORCEINLINE int aon_tmr2_touch_sts(void)
510 {
511  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_2_STS) & Bit1) >> 1) & 1);
512 }
513 
514 static FORCEINLINE void aon_tmr3_touch(int toggle)
515 {
516  WR_WORD(GLOBAL2_REG_AON_TIMER_3_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_3_CTL)|Bit1));
517 }
518 
519 static FORCEINLINE int aon_tmr3_touch_sts(void)
520 {
521  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_3_STS) & Bit1) >> 1) & 1);
522 }
523 
524 static FORCEINLINE void aon_tmr_irq_clr(uint32_t addr, uint32_t sts_addr)
525 {
526  WR_WORD(addr, Bit7 |Bit2 | RD_WORD(sts_addr));
527 }
528 
529 static FORCEINLINE int aon_tmr_irq_clr_sts(uint32_t addr)
530 {
531  return (((RD_WORD(addr) & Bit2) >> 2) & 1);
532 }
533 
534 static FORCEINLINE void aon_tmr0_irq_clr(void)
535 {
536  WR_WORD(GLOBAL2_REG_AON_TIMER_0_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_0_CTL)|Bit2));
537 }
538 
539 static FORCEINLINE int aon_tmr0_irq_clr_sts(void)
540 {
541  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_0_STS) & Bit2) >> 2) & 1);
542 }
543 
544 static FORCEINLINE void aon_tmr1_irq_clr(void)
545 {
546  WR_WORD(GLOBAL2_REG_AON_TIMER_1_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_1_CTL)|Bit2));
547 }
548 
549 static FORCEINLINE int aon_tmr1_irq_clr_sts(void)
550 {
551  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_1_STS) & Bit2) >> 2) & 1);
552 }
553 
554 static FORCEINLINE void aon_tmr2_irq_clr(void)
555 {
556  WR_WORD(GLOBAL2_REG_AON_TIMER_2_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_2_CTL)|Bit2));
557 }
558 
559 static FORCEINLINE int aon_tmr2_irq_clr_sts(void)
560 {
561  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_2_STS) & Bit2) >> 2) & 1);
562 }
563 
564 static FORCEINLINE void aon_tmr3_irq_clr(void)
565 {
566  WR_WORD(GLOBAL2_REG_AON_TIMER_3_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_3_CTL)|Bit2));
567 }
568 
569 static FORCEINLINE int aon_tmr3_irq_clr_sts(void)
570 {
571  return (((RD_WORD(GLOBAL2_REG_AON_TIMER_3_STS) & Bit2) >> 2) & 1);
572 }
573 
574 static FORCEINLINE void aon_tmr_manual_en(uint32_t addr)
575 {
576  WR_WORD(addr, (RD_WORD(addr) | Bit3));
577 }
578 
579 static FORCEINLINE int aon_tmr_manual_en_sts(uint32_t addr)
580 {
581  return ((RD_WORD(addr) & Bit3) >> 3);
582 }
583 
584 static FORCEINLINE void aon_tmr_manual_dis(uint32_t addr)
585 {
586  WR_WORD(addr, (RD_WORD(addr) & ~Bit3));
587 }
588 
589 static FORCEINLINE int aon_tmr_manual_dis_sts(uint32_t addr)
590 {
591  return ((RD_WORD(addr) & Bit3) >> 3);
592 }
593 
594 static FORCEINLINE void aon_tmr_manual_tick_en(uint32_t addr)
595 {
596  WR_WORD(addr, (RD_WORD(addr) | Bit4));
597 }
598 
599 static FORCEINLINE int aon_tmr_manual_tick_en_sts(uint32_t addr)
600 {
601  return (((RD_WORD(addr) & Bit4) >> 4) & 1);
602 }
603 
604 static FORCEINLINE void aon_tmr_manual_tick_dis(uint32_t addr)
605 {
606  WR_WORD(addr, (RD_WORD(addr) & ~Bit4));
607 }
608 
609 static FORCEINLINE int aon_tmr_manual_tick_dis_sts(uint32_t addr)
610 {
611  return (((RD_WORD(addr) & Bit4) >> 4) & 1);
612 }
613 
614 static FORCEINLINE void aon_tmr_wup_en(int id)
615 {
616  WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, (RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL)|(1<<id)));
617 }
618 
619 static FORCEINLINE void aon_tmr_wup_dis(int id)
620 {
621  WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, (RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL)&~(1<<id)));
622 }
623 
624 static FORCEINLINE void aon_tmr_int_clk_en(void)
625 {
626  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, (RD_WORD(GLOBAL_REG_CLK_ENABLE_1)|GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_AON_TIMER_INTR_CLK));
627 }
628 
629 static FORCEINLINE void aon_tmr_int_clk_dis(void)
630 {
631  WR_WORD(GLOBAL_REG_CLK_ENABLE_1, (RD_WORD(GLOBAL_REG_CLK_ENABLE_1)&~GLOBAL_REG_CLK_ENABLE_1_CTL_CLK_ENABLE_1_AON_TIMER_INTR_CLK));
632 }
633 
634 static FORCEINLINE uint32_t aon_tmr_int_status(void)
635 {
636  return (RD_WORD(GLOBAL2_REG_AON_TIMER_INTR_STATUS));
637 }
638 
639 static FORCEINLINE uint32_t aon_tmr_int_mask_status(void)
640 {
641  return (RD_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_STATUS));
642 }
643 
644 static FORCEINLINE void aon_tmr_int_clear(uint32_t status)
645 {
646  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_CLEAR, status);
647 }
648 
649 static FORCEINLINE void aon_tmr_int_set(int idx)
650 {
651 
652  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_SET, (1 << idx));
653 }
654 
655 static FORCEINLINE void aon_tmr_int_mask_set(int idx)
656 {
657  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_SET, (1 << idx));
658 }
659 
660 static FORCEINLINE void aon_tmr_cap_int_mask_set(int idx)
661 {
662  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_SET, (1 << AON_TMR2_INT_CAP0 << idx));
663 }
664 
665 static FORCEINLINE void aon_tmr_emit_int_mask_set(int idx)
666 {
667  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_SET, (1 << AON_TMR2_INT_EMIT0 << idx));
668 }
669 
670 static FORCEINLINE void aon_tmr_int_mask_clear(int idx)
671 {
672  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_CLEAR, (1 << idx));
673 }
674 
675 static FORCEINLINE void aon_tmr_cap_int_mask_clear(int idx)
676 {
677  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_CLEAR, (1 << AON_TMR2_INT_CAP0 << idx));
678 }
679 
680 static FORCEINLINE void aon_tmr_emit_int_mask_clear(int idx)
681 {
682  WR_WORD(GLOBAL2_REG_AON_TIMER_INTR_MASK_CLEAR, (1 << AON_TMR2_INT_EMIT0 << idx));
683 }
684 
685 static FORCEINLINE void aon_tmr_cap_clk_en(void)
686 {
687  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)|AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_CAP_CLK_EN));
688 }
689 
690 static FORCEINLINE void aon_tmr_cap_clk_dis(void)
691 {
692  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL)&~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_CAP_CLK_EN));
693 }
694 
695 static FORCEINLINE void aon_tmr_cap_rise_en(int idx)
696 {
697  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)|(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_CAP_SIG_REDGE_EN_SHIFT << idx)));
698 }
699 
700 static FORCEINLINE void aon_tmr_cap_rise_dis(int idx)
701 {
702  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)&~(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_CAP_SIG_REDGE_EN_SHIFT << idx)));
703 }
704 
705 static FORCEINLINE void aon_tmr_cap_fall_en(int idx)
706 {
707  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)|(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_CAP_SIG_FEDGE_EN_SHIFT << idx)));
708 }
709 
710 static FORCEINLINE void aon_tmr_cap_fall_dis(int idx)
711 {
712  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)&~(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_CAP_SIG_FEDGE_EN_SHIFT << idx)));
713 }
714 
715 static FORCEINLINE void aon_tmr_cap_sig(int idx, int hw_id)
716 {
717  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, ((RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL) & ~(0xFF << (16 + (idx << 3)))) | ((hw_id &0xFF) << (16 + (idx << 3)))));
718 }
719 
720 static FORCEINLINE uint32_t aon_tmr_cap_read_tick(int idx)
721 {
722  return (RD_WORD(GLOBAL_REG_AON_TIMER2_CAP_VAL_0 + (idx << 2)));
723 }
724 
725 static FORCEINLINE void aon_tmr_emit_clk_en(void)
726 {
727  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL) |AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_EMIT_CLK_EN));
728 }
729 
730 static FORCEINLINE void aon_tmr_emit_clk_dis(void)
731 {
732  WR_WORD(AON_REG_AON_TIMER_CLK_CTRL, (RD_WORD(AON_REG_AON_TIMER_CLK_CTRL) &~AON_REG_AON_TIMER_CLK_CTRL_CTL_AON_TIMER2_EMIT_CLK_EN));
733 }
734 
735 static FORCEINLINE void aon_tmr_emit_en(int idx)
736 {
737  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)|(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_EN_SHIFT << idx)));
738 }
739 
740 static FORCEINLINE void aon_tmr_emit_dis(int idx)
741 {
742  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)&~(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_EN_SHIFT << idx)));
743 }
744 
745 static FORCEINLINE void aon_tmr_emit_auto_clr_en(int idx)
746 {
747  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)|(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_AUTO_CLR_SHIFT << idx)));
748 }
749 
750 static FORCEINLINE void aon_tmr_emit_auto_clr_dis(int idx)
751 {
752  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)&~(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_AUTO_CLR_SHIFT << idx)));
753 }
754 
755 static FORCEINLINE void aon_tmr_emit_touch_clr_en(int idx)
756 {
757  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)|
758  (1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_TOUCH_CLR_EMIT_SHIFT << idx)));
759 }
760 
761 static FORCEINLINE void aon_tmr_emit_touch_clr_dis(int idx)
762 {
763  WR_WORD(AON_REG_AON_TIMER2_MISC_CTRL, (RD_WORD(AON_REG_AON_TIMER2_MISC_CTRL)&
764  ~(1 << AON_REG_AON_TIMER2_MISC_CTRL_CTL_AON_TIMER2_EMIT_TOUCH_CLR_EMIT_SHIFT << idx)));
765 }
766 
767 static FORCEINLINE void aon_tmr_emit_set_tick(int idx, uint32_t tick)
768 {
769  WR_WORD((AON_REG_AON_TIMER2_EMIT_VAL_0 + (idx << 2)), tick);
770 }
771 
772 static FORCEINLINE void aon_tmr_emit_wup_en(int idx)
773 {
774  WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, (RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL)|(1 << 4 << idx)));
775 }
776 
777 static FORCEINLINE void aon_tmr_emit_wup_dis(int idx)
778 {
779  WR_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL, (RD_WORD(AON_REG_AON_TIMER_WAKE_UP_SEL)&~(1 << 4 << idx)));
780 }
781 
782 static FORCEINLINE void aon_tmr_emit_man_clr(int idx)
783 {
784  WR_WORD(GLOBAL2_REG_AON_TIMER_2_CTL, (RD_WORD(GLOBAL2_REG_AON_TIMER_2_CTL)|(1 << 16 << idx)));
785 }
786 /*
787  * Inline Timer Functions
788  ****************************************************************************************
789  */
790 static FORCEINLINE void tmr_all_enable(void)
791 {
792  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL) | Bit0));
793 }
794 
795 static FORCEINLINE void tmr_intr_reset(int en)
796 {
797  uint32_t reg = RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL);
798  if (en) {
799  reg |= Bit1;
800  } else {
801  reg &= ~Bit1;
802  }
803  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, reg);
804 }
805 
806 static FORCEINLINE void tmr_add_all_enable(void)
807 {
808  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL) | Bit0));
809 }
810 
811 static FORCEINLINE void tmr_add_intr_reset(int en)
812 {
813  uint32_t reg = RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL);
814  if (en) {
815  reg |= Bit1;
816  } else {
817  reg &= ~Bit1;
818  }
819  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, reg);
820 }
821 
822 static FORCEINLINE void tmr_manual_en(int id)
823 {
824  if (id < TMR6_ID)
825  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL) | (1 << 16 << id)));
826  else
827  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL) | (1 << (16 + id - 6))));
828 }
829 
830 static FORCEINLINE void tmr_manual_dis(int id)
831 {
832  if (id < TMR6_ID)
833  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL) & ~(1 << 16 << id)));
834  else
835  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL) & ~(1 << (16 + id - 6))));
836 }
837 
838 static FORCEINLINE void tmr_manual_tick(int id)
839 {
840  if (id < TMR6_ID)
841  WR_WORD(TIMERS_REGS_MANUAL_TICK, (1 << id));
842  else
843  WR_WORD(TIMERS_REGS_MANUAL_TICK, (1 << (8 + id -6)));
844 }
845 
846 static FORCEINLINE void tmr_reload_en(int id)
847 {
848  if (id < TMR6_ID)
849  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL) | (1 << 24 << id)));
850  else
851  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL) | (1 << (24 + id - 6))));
852 }
853 
854 static FORCEINLINE void tmr_reload_dis(int id)
855 {
856  if (id < TMR6_ID)
857  WR_WORD(TIMERS_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_REGS_TIMERS_MISC_CTRL) & ~(1 << 24 << id)));
858  else
859  WR_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL, (RD_WORD(TIMERS_ADD_REGS_TIMERS_MISC_CTRL) & ~(1 << (24 + id - 6))));
860 }
861 
862 static FORCEINLINE void tmr_touch(int id)
863 {
864  if (id < TMR6_ID)
865  WR_WORD(TIMERS_REGS_TOUCH, (1 << id));
866  else
867  WR_WORD(TIMERS_REGS_TOUCH, (1 << (8 + id -6)));
868 }
869 
870 static FORCEINLINE void tmr_enable(uint32_t addr)
871 {
872  WR_WORD(addr, (RD_WORD(addr) | Bit0));
873 }
874 
875 static FORCEINLINE void tmr0_enable(void)
876 {
877  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | Bit0));
878 }
879 
880 static FORCEINLINE void tmr1_enable(void)
881 {
882  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | Bit0));
883 }
884 
885 static FORCEINLINE void tmr2_enable(void)
886 {
887  WR_WORD(TIMERS_REGS_BASIC_TIMER_2_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_2_CTRL) | Bit0));
888 }
889 
890 static FORCEINLINE void tmr3_enable(void)
891 {
892  WR_WORD(TIMERS_REGS_BASIC_TIMER_3_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_3_CTRL) | Bit0));
893 }
894 
895 static FORCEINLINE void tmr4_enable(void)
896 {
897  WR_WORD(TIMERS_REGS_BASIC_TIMER_4_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_4_CTRL) | Bit0));
898 }
899 
900 static FORCEINLINE void tmr5_enable(void)
901 {
902  WR_WORD(TIMERS_REGS_BASIC_TIMER_5_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_5_CTRL) | Bit0));
903 }
904 
905 static FORCEINLINE void tmr_disable(uint32_t addr)
906 {
907  WR_WORD(addr, (RD_WORD(addr) & ~Bit0));
908 }
909 
910 static FORCEINLINE void tmr0_disable(void)
911 {
912  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~Bit0));
913 }
914 
915 static FORCEINLINE void tmr1_disable(void)
916 {
917  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~Bit0));
918 }
919 
920 static FORCEINLINE void tmr2_disable(void)
921 {
922  WR_WORD(TIMERS_REGS_BASIC_TIMER_2_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_2_CTRL) & ~Bit0));
923 }
924 
925 static FORCEINLINE void tmr3_disable(void)
926 {
927  WR_WORD(TIMERS_REGS_BASIC_TIMER_3_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_3_CTRL) & ~Bit0));
928 }
929 
930 static FORCEINLINE void tmr4_disable(void)
931 {
932  WR_WORD(TIMERS_REGS_BASIC_TIMER_4_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_4_CTRL) & ~Bit0));
933 }
934 
935 static FORCEINLINE void tmr5_disable(void)
936 {
937  WR_WORD(TIMERS_REGS_BASIC_TIMER_5_CTRL, (RD_WORD(TIMERS_REGS_BASIC_TIMER_5_CTRL) & ~Bit0));
938 }
939 
940 static FORCEINLINE void tmr_init_tick(uint32_t addr, uint32_t tick)
941 {
942  WR_WORD(addr, tick);
943 }
944 
945 static FORCEINLINE uint32_t tmr_read_init_tick(uint32_t addr)
946 {
947  return RD_WORD(addr);
948 }
949 
950 static FORCEINLINE void tmr0_init_tick(uint32_t tick)
951 {
952  WR_WORD(TIMERS_REGS_ADV_TIMER_0_INIT_VAL, tick);
953 }
954 
955 static FORCEINLINE uint32_t tmr0_read_init_tick(void)
956 {
957  return RD_WORD(TIMERS_REGS_ADV_TIMER_0_INIT_VAL);
958 }
959 
960 static FORCEINLINE void tmr1_init_tick(uint32_t tick)
961 {
962  WR_WORD(TIMERS_REGS_ADV_TIMER_1_INIT_VAL, tick);
963 }
964 
965 static FORCEINLINE uint32_t tmr1_read_init_tick(void)
966 {
967  return RD_WORD(TIMERS_REGS_ADV_TIMER_1_INIT_VAL);
968 }
969 
970 static FORCEINLINE void tmr2_init_tick(uint32_t tick)
971 {
972  WR_WORD(TIMERS_REGS_BASIC_TIMER_2_INIT_VAL, tick);
973 }
974 
975 static FORCEINLINE uint32_t tmr2_read_init_tick(void)
976 {
977  return RD_WORD(TIMERS_REGS_BASIC_TIMER_2_INIT_VAL);
978 }
979 
980 static FORCEINLINE void tmr3_init_tick(uint32_t tick)
981 {
982  WR_WORD(TIMERS_REGS_BASIC_TIMER_3_INIT_VAL, tick);
983 }
984 
985 static FORCEINLINE uint32_t tmr3_read_init_tick(void)
986 {
987  return RD_WORD(TIMERS_REGS_BASIC_TIMER_3_INIT_VAL);
988 }
989 
990 static FORCEINLINE void tmr4_init_tick(uint32_t tick)
991 {
992  WR_WORD(TIMERS_REGS_BASIC_TIMER_4_INIT_VAL, tick);
993 }
994 
995 static FORCEINLINE uint32_t tmr4_read_init_tick(void)
996 {
997  return RD_WORD(TIMERS_REGS_BASIC_TIMER_4_INIT_VAL);
998 }
999 
1000 static FORCEINLINE void tmr5_init_tick(uint32_t tick)
1001 {
1002  WR_WORD(TIMERS_REGS_BASIC_TIMER_5_INIT_VAL, tick);
1003 }
1004 
1005 static FORCEINLINE uint32_t tmr5_read_init_tick(void)
1006 {
1007  return RD_WORD(TIMERS_REGS_BASIC_TIMER_5_INIT_VAL);
1008 }
1009 
1010 static FORCEINLINE uint32_t tmr_read_tick(uint32_t addr)
1011 {
1012  return RD_WORD(addr);
1013 }
1014 
1015 static FORCEINLINE uint32_t tmr0_read_tick(void)
1016 {
1017  return RD_WORD(TIMERS_REGS_ADV_TIMER_0_CURR_VAL);
1018 }
1019 
1020 static FORCEINLINE uint32_t tmr1_read_tick(void)
1021 {
1022  return RD_WORD(TIMERS_REGS_ADV_TIMER_1_CURR_VAL);
1023 }
1024 
1025 static FORCEINLINE uint32_t tmr2_read_tick(void)
1026 {
1027  return RD_WORD(TIMERS_REGS_BASIC_TIMER_2_CURR_VAL);
1028 }
1029 
1030 static FORCEINLINE uint32_t tmr3_read_tick(void)
1031 {
1032  return RD_WORD(TIMERS_REGS_BASIC_TIMER_3_CURR_VAL);
1033 }
1034 
1035 static FORCEINLINE uint32_t tmr4_read_tick(void)
1036 {
1037  return RD_WORD(TIMERS_REGS_BASIC_TIMER_4_CURR_VAL);
1038 }
1039 
1040 static FORCEINLINE uint32_t tmr5_read_tick(void)
1041 {
1042  return RD_WORD(TIMERS_REGS_BASIC_TIMER_5_CURR_VAL);
1043 }
1044 
1045 static FORCEINLINE void tmr_int_clear(int id)
1046 {
1047  if (id < TMR6_ID)
1048  WR_WORD(TIMERS_REGS_TIMEOUT_IRQ_CLR, (1 << id));
1049  else
1050  WR_WORD(TIMERS_REGS_TIMEOUT_IRQ_CLR, (1 << (8 + id - 6)));
1051 
1052 }
1053 
1054 static INLINE void tmr_systick_enable(uint32_t init_count)
1055 {
1056  uint32_t reg = RD_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL);
1057  reg &= ~(TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_FINECNT_LMT);
1058  reg |= (init_count & TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_FINECNT_LMT_MASK) << TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_FINECNT_LMT_SHIFT;
1059  reg |= TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_EN;
1060  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1061 
1062  reg = RD_WORD(AON_REG_SYSTICK_AON_CTRL);
1063  reg |= AON_REG_SYSTICK_AON_CTRL_CTL_SYSTICK_AON_EN;
1064  WR_WORD(AON_REG_SYSTICK_AON_CTRL, reg);
1065 }
1066 
1067 static INLINE void tmr_systick_disable(void)
1068 {
1069  uint32_t reg = RD_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL);
1070  reg &= ~(TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_EN);
1071  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1072 }
1073 
1074 static FORCEINLINE uint32_t tmr_systick_coarse_count(void)
1075 {
1076  return RD_WORD(TIMERS_REGS_SYSTICK_CURR_COARSECNT);
1077 }
1078 
1079 static FORCEINLINE uint32_t tmr_systick_fine_count(void)
1080 {
1081  return RD_WORD(TIMERS_REGS_SYSTICK_CURR_FINECNT);
1082 }
1083 
1084 static INLINE void tmr_systick_sleep(void)
1085 {
1086  uint32_t reg = RD_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL);
1087  reg |= TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_GO_TO_SLEEP;
1088  reg &= ~TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_WAKEUP;
1089  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1091  while (!(RD_WORD(TIMERS_REGS_SYSTICK_INTR_STATUS) & 0x2));
1093  WR_WORD(TIMERS_REGS_SYSTICK_INTR_CLEAR, 0x2);
1094 
1095 }
1096 
1097 static INLINE void tmr_systick_wup(void)
1098 {
1099  uint32_t reg = RD_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL);
1100  reg &= ~TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_GO_TO_SLEEP;
1101  reg |= TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_WAKEUP;
1102  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1104  while (!(RD_WORD(TIMERS_REGS_SYSTICK_INTR_STATUS) & 0x1));
1106  WR_WORD(TIMERS_REGS_SYSTICK_INTR_CLEAR, 0x1);
1107 
1108 }
1109 
1110 static INLINE void tmr_systick_reset(void)
1111 {
1112  uint32_t reg = RD_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL);
1113  reg |= TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_RESET;
1114  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1115  reg &= ~TIMERS_REGS_SYSTICK_MISC_CTRL_CTL_SYSTICK_RESET;
1116  WR_WORD(TIMERS_REGS_SYSTICK_MISC_CTRL, reg);
1117 }
1118 
1119 static INLINE void tmr_systick_clk_ratio(uint32_t frac, uint32_t integer)
1120 {
1121  uint32_t reg = (frac & TIMERS_REGS_SYSTICK_CLK_RATIO_CTL_FRAC_SYSCLK_IN_SLPCLK_MASK);
1122  reg |= (integer & TIMERS_REGS_SYSTICK_CLK_RATIO_CTL_INT_SYSCLK_IN_SLPCLK_MASK) << TIMERS_REGS_SYSTICK_CLK_RATIO_CTL_INT_SYSCLK_IN_SLPCLK_SHIFT;
1123  WR_WORD(TIMERS_REGS_SYSTICK_CLK_RATIO, reg);
1124 }
1125 
1126 static FORCEINLINE void tmr_systick_clk_ratio_set(uint32_t ratio)
1127 {
1128  WR_WORD(TIMERS_REGS_SYSTICK_CLK_RATIO, ratio);
1129 }
1130 
1131 static FORCEINLINE uint32_t tmr_systick_clk_ratio_get(void)
1132 {
1133  return RD_WORD(TIMERS_REGS_SYSTICK_CLK_RATIO);
1134 }
1135 
1136 
1137 static FORCEINLINE uint32_t tmr_systick_slp_clk_count(void)
1138 {
1139  return RD_WORD(TIMERS_REGS_SYSTICK_SLP_CLK_CNT);
1140 }
1141 
1142 static FORCEINLINE uint32_t tmr_systick_slp_fine_count(void)
1143 {
1144  return RD_WORD(TIMERS_REGS_SYSTICK_SLP_FINE_CNT);
1145 }
1146 
1147 static FORCEINLINE uint32_t tmr_systick_slp_coarse_count(void)
1148 {
1149  return RD_WORD(TIMERS_REGS_SYSTICK_SLP_COARSE_CNT);
1150 }
1151 
1152 static FORCEINLINE uint32_t tmr_systick_store_coarse_count(void)
1153 {
1154  return RD_WORD(TIMERS_REGS_SYSTICK_STORED_COARSE_CNT);
1155 }
1156 
1157 static FORCEINLINE uint32_t tmr_systick_store_fine_count(void)
1158 {
1159  return RD_WORD(TIMERS_REGS_SYSTICK_STORED_FINE_CNT);
1160 }
1161 
1162 static FORCEINLINE uint32_t tmr_adv_int_status(uint32_t addr)
1163 {
1164  return RD_WORD(addr);
1165 }
1166 
1167 static FORCEINLINE uint32_t tmr0_adv_int_status(void)
1168 {
1169  return RD_WORD(TIMERS_REGS_TIMER0_MISC_INTR_STATUS);
1170 }
1171 
1172 static FORCEINLINE uint32_t tmr1_adv_int_status(void)
1173 {
1174  return RD_WORD(TIMERS_REGS_TIMER1_MISC_INTR_STATUS);
1175 }
1176 
1177 static FORCEINLINE uint32_t tmr_adv_int_mask_status(uint32_t addr)
1178 {
1179  return RD_WORD(addr);
1180 }
1181 
1182 static FORCEINLINE uint32_t tmr0_adv_int_mask_status(void)
1183 {
1184  return RD_WORD(TIMERS_REGS_TIMER0_MISC_INTR_MASK_STATUS);
1185 }
1186 
1187 static FORCEINLINE uint32_t tmr1_adv_int_mask_status(void)
1188 {
1189  return RD_WORD(TIMERS_REGS_TIMER1_MISC_INTR_MASK_STATUS);
1190 }
1191 
1192 static FORCEINLINE void tmr_adv_int_clr_all(uint32_t addr)
1193 {
1194  WR_WORD(addr, 0x3FFF);
1195 }
1196 
1197 static FORCEINLINE void tmr0_adv_int_clr_all(void)
1198 {
1199  WR_WORD(TIMERS_REGS_TIMER0_MISC_INTR_CLEAR, 0x3FFF);
1200 }
1201 
1202 static FORCEINLINE void tmr1_adv_int_clr_all(void)
1203 {
1204  WR_WORD(TIMERS_REGS_TIMER1_MISC_INTR_CLEAR, 0x3FFF);
1205 }
1206 
1207 static FORCEINLINE void tmr_adv_int_clr(uint32_t addr, uint32_t mask)
1208 {
1209  WR_WORD(addr, mask);
1210 }
1211 
1212 static FORCEINLINE void tmr0_adv_int_clr(uint32_t mask)
1213 {
1214  WR_WORD(TIMERS_REGS_TIMER0_MISC_INTR_CLEAR, mask);
1215 }
1216 
1217 static FORCEINLINE void tmr1_adv_int_clr(uint32_t mask)
1218 {
1219  WR_WORD(TIMERS_REGS_TIMER1_MISC_INTR_CLEAR, mask);
1220 }
1221 
1222 static FORCEINLINE void tmr_adv_int_mask(uint32_t addr, uint32_t bit)
1223 {
1224  WR_WORD(addr, (1 << bit));
1225 }
1226 
1227 static FORCEINLINE void tmr0_adv_int_mask(uint32_t bit)
1228 {
1229  WR_WORD(TIMERS_REGS_TIMER0_MISC_INTR_MASK_SET, (1 << bit));
1230 }
1231 
1232 static FORCEINLINE void tmr1_adv_int_mask(uint32_t bit)
1233 {
1234  WR_WORD(TIMERS_REGS_TIMER1_MISC_INTR_MASK_SET, (1 << bit));
1235 }
1236 
1237 static FORCEINLINE void tmr_adv_int_mask_all(uint32_t addr)
1238 {
1239  WR_WORD(addr, 0x3FFF);
1240 }
1241 
1242 static FORCEINLINE void tmr0_adv_int_mask_all(void)
1243 {
1244  WR_WORD(TIMERS_REGS_TIMER0_MISC_INTR_MASK_SET, 0x3FFF);
1245 }
1246 
1247 static FORCEINLINE void tmr1_adv_int_mask_all(void)
1248 {
1249  WR_WORD(TIMERS_REGS_TIMER1_MISC_INTR_MASK_SET, 0x3FFF);
1250 }
1251 
1252 static FORCEINLINE void tmr_adv_int_unmask(uint32_t addr, uint32_t bit)
1253 {
1254  WR_WORD(addr, (1 << bit));
1255 }
1256 
1257 static FORCEINLINE void tmr0_adv_int_unmask(uint32_t bit)
1258 {
1259  WR_WORD(TIMERS_REGS_TIMER0_MISC_INTR_MASK_CLEAR, (1 << bit));
1260 }
1261 
1262 static FORCEINLINE void tmr1_adv_int_unmask(uint32_t bit)
1263 {
1264  WR_WORD(TIMERS_REGS_TIMER1_MISC_INTR_MASK_CLEAR, (1 << bit));
1265 }
1266 
1267 static FORCEINLINE void tmr_adv_cap_rise_en(uint32_t addr, int idx)
1268 {
1269  WR_WORD(addr, (RD_WORD(addr) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1270 }
1271 
1272 static FORCEINLINE void tmr0_adv_cap_rise_en(int idx)
1273 {
1274  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1275 }
1276 
1277 static FORCEINLINE void tmr1_adv_cap_rise_en(int idx)
1278 {
1279  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1280 }
1281 
1282 static FORCEINLINE void tmr_adv_cap_rise_dis(uint32_t addr, int idx)
1283 {
1284  WR_WORD(addr, (RD_WORD(addr) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1285 }
1286 
1287 static FORCEINLINE void tmr0_adv_cap_rise_dis(uint32_t addr, int idx)
1288 {
1289  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1290 }
1291 
1292 static FORCEINLINE void tmr1_adv_cap_rise_dis(uint32_t addr, int idx)
1293 {
1294  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_REDGE_ENABLE_SHIFT << idx)));
1295 }
1296 
1297 static FORCEINLINE void tmr_adv_cap_fall_en(uint32_t addr, int idx)
1298 {
1299  WR_WORD(addr, (RD_WORD(addr) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1300 }
1301 
1302 static FORCEINLINE void tmr0_adv_cap_fall_en(uint32_t addr, int idx)
1303 {
1304  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1305 }
1306 
1307 static FORCEINLINE void tmr1_adv_cap_fall_en(uint32_t addr, int idx)
1308 {
1309  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1310 }
1311 
1312 static FORCEINLINE void tmr_adv_cap_fall_dis(uint32_t addr, int idx)
1313 {
1314  WR_WORD(addr, (RD_WORD(addr) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1315 }
1316 
1317 static FORCEINLINE void tmr0_adv_cap_fall_dis(uint32_t addr, int idx)
1318 {
1319  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1320 }
1321 
1322 static FORCEINLINE void tmr1_adv_cap_fall_dis(uint32_t addr, int idx)
1323 {
1324  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_CAP_FEDGE_ENABLE_SHIFT << idx)));
1325 }
1326 
1327 static FORCEINLINE void tmr_adv_cap_sig(uint32_t addr, int idx, uint8_t sig_id)
1328 {
1329  WR_WORD(addr, ((RD_WORD(addr) & ~(0xFF << (idx << 3))) | (((sig_id & 0xFF) << (idx << 3)))));
1330 }
1331 
1332 static FORCEINLINE void tmr0_adv_cap_sig(int idx, uint8_t sig_id)
1333 {
1334  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CAP_SIG_SEL, ((RD_WORD(TIMERS_REGS_ADV_TIMER_0_CAP_SIG_SEL) & ~(0xFF << (idx << 3))) | (((sig_id & 0xFF) << (idx << 3)))));
1335 }
1336 
1337 static FORCEINLINE void tmr1_adv_cap_sig(int idx, uint8_t sig_id)
1338 {
1339  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CAP_SIG_SEL, ((RD_WORD(TIMERS_REGS_ADV_TIMER_1_CAP_SIG_SEL) & ~(0xFF << (idx << 3))) | (((sig_id & 0xFF) << (idx << 3)))));
1340 }
1341 
1342 static FORCEINLINE uint32_t tmr_adv_cap_tick(uint32_t addr, int idx)
1343 {
1344  return RD_WORD(addr + (idx * 4));
1345 }
1346 
1347 static FORCEINLINE uint32_t tmr0_adv_cap_tick(int idx)
1348 {
1349  return RD_WORD(TIMERS_REGS_ADV_TIMER_0_CAP_VAL_0 + (idx * 4));
1350 }
1351 
1352 static FORCEINLINE uint32_t tmr1_adv_cap_tick(int idx)
1353 {
1354  return RD_WORD(TIMERS_REGS_ADV_TIMER_1_CAP_VAL_0 + (idx * 4));
1355 }
1356 
1357 static FORCEINLINE void tmr_adv_emit_en(uint32_t addr, int idx)
1358 {
1359 
1360  if ((idx == 8) || (idx == 9)) {
1361  WR_WORD(addr, (RD_WORD(addr) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1362  } else {
1363  WR_WORD(addr, (RD_WORD(addr) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE_SHIFT + idx))));
1364  }
1365 }
1366 
1367 static FORCEINLINE void tmr0_adv_emit_en(int idx)
1368 {
1369  if ((idx == 8) || (idx == 9)) {
1370  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1371  } else {
1372  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE_SHIFT + idx))));
1373  }
1374 
1375 }
1376 
1377 static FORCEINLINE void tmr1_adv_emit_en(int idx)
1378 {
1379  if ((idx == 8) || (idx == 9)) {
1380  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1381  } else {
1382  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_EMIT_ENABLE_SHIFT + idx))));
1383  }
1384 }
1385 
1386 static FORCEINLINE void tmr_adv_emit_dis(uint32_t addr, int idx)
1387 {
1388  if ((idx == 8) || (idx == 9)) {
1389  WR_WORD(addr, (RD_WORD(addr) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1390  } else {
1391  WR_WORD(addr, (RD_WORD(addr) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE_SHIFT + idx))));
1392  }
1393 }
1394 
1395 static FORCEINLINE void tmr0_adv_emit_dis(int idx)
1396 {
1397 
1398  if ((idx == 8) || (idx == 9)) {
1399  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1400  } else {
1401  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_EMIT_ENABLE_SHIFT + idx))));
1402  }
1403 }
1404 
1405 static FORCEINLINE void tmr1_adv_emit_dis(int idx)
1406 {
1407  if ((idx == 8) || (idx == 9)) {
1408  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_EMIT_ENABLE2_SHIFT + idx - 8))));
1409  } else {
1410  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_EMIT_ENABLE_SHIFT + idx))));
1411  }
1412 }
1413 
1414 static FORCEINLINE void tmr_adv_emit_touch_clr_en(uint32_t addr, int idx)
1415 {
1416  if ((idx == 8) || (idx == 9)) {
1417  WR_WORD(addr, (RD_WORD(addr) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT2_SHIFT + idx - 8))));
1418  } else {
1419  WR_WORD(addr, (RD_WORD(addr) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1420  }
1421 }
1422 
1423 static FORCEINLINE void tmr0_adv_emit_touch_clr_en(int idx)
1424 {
1425  if ((idx == 8) || (idx == 9)) {
1426  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT2_SHIFT + idx - 8))));
1427  } else {
1428  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1429  }
1430 }
1431 
1432 static FORCEINLINE void tmr1_adv_emit_touch_clr_en(int idx)
1433 {
1434  if ((idx == 8) || (idx == 9)) {
1435  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_TOUCH_CLR_EMIT2_SHIFT + idx - 8))));
1436  } else {
1437  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) | (1 << TIMERS_REGS_ADV_TIMER_1_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1438  }
1439 }
1440 
1441 
1442 static FORCEINLINE void tmr_adv_emit_touch_clr_dis(uint32_t addr, int idx)
1443 {
1444  if ((idx == 8) || (idx == 9)) {
1445  WR_WORD(addr, (RD_WORD(addr) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT2_SHIFT + idx - 8))));
1446  } else {
1447  WR_WORD(addr, (RD_WORD(addr) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1448  }
1449 }
1450 
1451 static FORCEINLINE void tmr0_adv_emit_touch_clr_dis(int idx)
1452 {
1453  if ((idx == 8) || (idx == 9)) {
1454  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT_SHIFT + idx - 8))));
1455  } else {
1456  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_0_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1457  }
1458 }
1459 
1460 static FORCEINLINE void tmr1_adv_emit_touch_clr_dis(int idx)
1461 {
1462  if ((idx == 8) || (idx == 9)) {
1463  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << (TIMERS_REGS_ADV_TIMER_1_CTRL_TOUCH_CLR_EMIT_SHIFT + idx - 8))));
1464  } else {
1465  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL) & ~(1 << TIMERS_REGS_ADV_TIMER_1_CTRL_TOUCH_CLR_EMIT_SHIFT << idx)));
1466  }
1467 }
1468 
1469 static FORCEINLINE void tmr_adv_emit_auto_clr_en(uint32_t addr, int idx)
1470 {
1471  WR_WORD(addr, (RD_WORD(addr) | (1 << idx)));
1472 }
1473 
1474 static FORCEINLINE void tmr0_adv_emit_auto_clr_en(int idx)
1475 {
1476  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL1, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL1) | (1 << idx)));
1477 }
1478 
1479 static FORCEINLINE void tmr1_adv_emit_auto_clr_en(int idx)
1480 {
1481  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL1, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL1) | (1 << idx)));
1482 }
1483 
1484 static FORCEINLINE void tmr_adv_emit_auto_clr_dis(uint32_t addr, int idx)
1485 {
1486  WR_WORD(addr, (RD_WORD(addr) & ~(1 << idx)));
1487 }
1488 
1489 static FORCEINLINE void tmr0_adv_emit_auto_clr_dis(int idx)
1490 {
1491  WR_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL1, (RD_WORD(TIMERS_REGS_ADV_TIMER_0_CTRL1) & ~(1 << idx)));
1492 }
1493 
1494 static FORCEINLINE void tmr1_adv_emit_auto_clr_dis(int idx)
1495 {
1496  WR_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL1, (RD_WORD(TIMERS_REGS_ADV_TIMER_1_CTRL1) & ~(1 << idx)));
1497 }
1498 
1499 static FORCEINLINE void tmr_adv_emit_manual_clr(uint32_t addr, int idx)
1500 {
1501  WR_WORD(addr, (1 << idx));
1502 }
1503 
1504 static FORCEINLINE void tmr0_adv_emit_manual_clr(int idx)
1505 {
1506  WR_WORD(TIMERS_REGS_ADV_TIMER_0_EMIT_CLR, (1 << idx));
1507 }
1508 
1509 static FORCEINLINE void tmr1_adv_emit_manual_clr(int idx)
1510 {
1511  WR_WORD(TIMERS_REGS_ADV_TIMER_1_EMIT_CLR, (1 << idx));
1512 }
1513 
1514 static FORCEINLINE int tmr_adv_emit_status(uint32_t addr, int idx)
1515 {
1516  return ((RD_WORD(addr) >> idx) & 1);
1517 }
1518 
1519 static FORCEINLINE int tmr0_adv_emit_status(int idx)
1520 {
1521  return ((RD_WORD(TIMERS_REGS_ADV_TIMER_0_EMIT_SIG_STATUS) >> idx) & 1);
1522 }
1523 
1524 static FORCEINLINE int tmr1_adv_emit_status(int idx)
1525 {
1526  return ((RD_WORD(TIMERS_REGS_ADV_TIMER_1_EMIT_SIG_STATUS) >> idx) & 1);
1527 }
1528 
1529 static FORCEINLINE void tmr_adv_emit_set_tick(uint32_t addr, int idx, uint32_t tick)
1530 {
1531  if ((idx == 8) || (idx == 9)) {
1532  WR_WORD((addr + (idx *4) + 8), tick);
1533  } else {
1534  WR_WORD((addr + (idx *4)), tick);
1535  }
1536 
1537 }
1538 
1539 static FORCEINLINE void tmr0_adv_emit_set_tick(int idx, uint32_t tick)
1540 {
1541  if ((idx == 8) || (idx == 9)) {
1542  WR_WORD((TIMERS_REGS_ADV_TIMER_0_EMIT_0 + (idx *4) + 8), tick);
1543  } else {
1544  WR_WORD((TIMERS_REGS_ADV_TIMER_0_EMIT_0 + (idx *4)), tick);
1545  }
1546 
1547 }
1548 
1549 static FORCEINLINE void tmr1_adv_emit_set_tick(int idx, uint32_t tick)
1550 {
1551  if ((idx == 8) || (idx == 9)) {
1552  WR_WORD((TIMERS_REGS_ADV_TIMER_1_EMIT_0 + (idx *4) + 8), tick);
1553  } else {
1554  WR_WORD((TIMERS_REGS_ADV_TIMER_1_EMIT_0 + (idx *4)), tick);
1555  }
1556 }
1557 
1558 static FORCEINLINE void tmr_adv_emit_toggle_default(uint32_t addr, int idx, int val)
1559 {
1560  uint32_t reg = RD_WORD(addr);
1561  if (val) {
1562  reg |= 1 << (10 + idx);
1563  }else {
1564  reg &= ~(1 << (10 + idx));
1565  }
1566  WR_WORD(addr, reg);
1567 }
1568 
1569 static FORCEINLINE void tmr_adv_emit_toggle_pol(uint32_t addr, int idx, int val)
1570 {
1571  uint32_t reg = RD_WORD(addr);
1572  if (val) {
1573  reg |= 1 << (15 + idx);
1574  }else {
1575  reg &= ~(1 << (15 + idx));
1576  }
1577  WR_WORD(addr, reg);
1578 }
1579 
1580 static FORCEINLINE void tmr_adv_emit_sig_toggle(uint32_t addr, int idx, int val)
1581 {
1582  uint32_t reg = RD_WORD(addr);
1583  if (val) {
1584  reg |= 1 << (20 + idx);
1585  }else {
1586  reg &= ~(1 << (20 + idx));
1587  }
1588  WR_WORD(addr, reg);
1589 }
1590 
1591 static FORCEINLINE void tmr_adv_emit_sig_default(uint32_t addr, int idx, int val)
1592 {
1593  uint32_t reg = RD_WORD(addr);
1594  if (val) {
1595  reg |= 1 << idx;
1596  }else {
1597  reg &= ~(1 << idx);
1598  }
1599  WR_WORD(addr, reg);
1600 }
1601 
1602 static FORCEINLINE void tmr_smem_emit_en(uint32_t addr)
1603 {
1604  WR_WORD(addr, RD_WORD(addr) | TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_EN);
1605 }
1606 
1607 static FORCEINLINE void tmr_smem_emit_rst(uint32_t addr)
1608 {
1609  uint32_t reg = RD_WORD(addr);
1610  WR_WORD(addr, reg | TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_RESET);
1611  WR_WORD(addr, reg & ~TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_RESET);
1612 }
1613 
1614 
1615 static FORCEINLINE void tmr_smem_emit_dis(uint32_t addr)
1616 {
1617  WR_WORD(addr, RD_WORD(addr) & ~TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_EN);
1618 }
1619 
1620 static FORCEINLINE void tmr_smem_emit_set_max_num(uint32_t addr, uint32_t num)
1621 {
1622  WR_WORD(addr, (RD_WORD(addr) & ~TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_NUM_ENTRIES_M1)
1623  | ((num & TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_NUM_ENTRIES_M1_MASK) << TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_NUM_ENTRIES_M1_SHIFT));
1624 }
1625 static FORCEINLINE uint32_t tmr_smem_emit_get_max_num(uint32_t addr)
1626 {
1627  return (RD_WORD(addr) & TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_NUM_ENTRIES_M1) >> TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_NUM_ENTRIES_M1_SHIFT;
1628 }
1629 static FORCEINLINE void tmr_smem_emit_empty_th(uint32_t addr, uint32_t num)
1630 {
1631  WR_WORD(addr, (RD_WORD(addr) & ~TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_ALMOST_EMPTY_TH)
1632  | ((num & TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_ALMOST_EMPTY_TH_MASK) << TIMERS_REGS_EMIT_SHM_IF_CTRL_CTL_EMIT_SHM_IF_ALMOST_EMPTY_TH_SHIFT));
1633 }
1634 
1635 static FORCEINLINE void tmr_smem_emit_set_tick(uint32_t addr, uint32_t val)
1636 {
1637  WR_WORD(addr, val);
1638  RD_WORD(addr);
1639 }
1640 
1641 static FORCEINLINE uint32_t tmr_smem_emit_data_num(uint32_t addr)
1642 {
1643  uint32_t reg = RD_WORD(addr);
1644  uint32_t smem = (reg & TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_SHM)>>TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_SHM_SHIFT;
1645  uint32_t reg_fifo = (reg & TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_REG_FIFO)>>TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_REG_FIFO_SHIFT;
1646  uint32_t fifo = (reg & TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_FIFO)>>TIMERS_REGS_EMIT_SHM_NUM_VAL_STS_EMIT_SHM_IF_NUM_DATA_IN_FIFO_SHIFT;
1647  return smem + reg_fifo + fifo;
1648 }
1649 
1650 static FORCEINLINE void tmr_smem_cap_en(uint32_t addr)
1651 {
1652  WR_WORD(addr, RD_WORD(addr) | TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_EN);
1653 }
1654 
1655 static FORCEINLINE void tmr_smem_cap_dis(uint32_t addr)
1656 {
1657  WR_WORD(addr, RD_WORD(addr) & ~TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_EN);
1658 }
1659 
1660 static FORCEINLINE void tmr_smem_cap_set_max_num(uint32_t addr, uint32_t num)
1661 {
1662  WR_WORD(addr, (RD_WORD(addr) & ~TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_NUM_ENTRIES_M1)
1663  | ((num & TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_NUM_ENTRIES_M1_MASK) << TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_NUM_ENTRIES_M1_SHIFT));
1664 }
1665 
1666 static FORCEINLINE uint32_t tmr_smem_cap_get_max_num(uint32_t addr)
1667 {
1668  return (RD_WORD(addr) & TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_NUM_ENTRIES_M1) >> TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_NUM_ENTRIES_M1_SHIFT;
1669 }
1670 
1671 static FORCEINLINE void tmr_smem_cap_full_th(uint32_t addr, uint32_t num)
1672 {
1673  WR_WORD(addr, (RD_WORD(addr) & ~TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_ALMOST_FULL_TH)
1674  | ((num & TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_ALMOST_FULL_TH_MASK) << TIMERS_REGS_CAP_SHM_IF_CTRL_CTL_CAP_SHM_IF_ALMOST_FULL_TH_SHIFT));
1675 }
1676 
1677 static FORCEINLINE uint32_t tmr_smem_cap_tick(uint32_t addr)
1678 {
1679  return RD_WORD(addr);
1680 }
1681 
1682 static FORCEINLINE uint32_t tmr_smem_intr_status(uint32_t addr)
1683 {
1684  return RD_WORD(addr);
1685 }
1686 
1687 static FORCEINLINE uint32_t tmr_smem_intr_mask_status(void)
1688 {
1689  return RD_WORD(TIMERS_REGS_SHM_IF_INTR_MASK_STATUS);
1690 }
1691 
1692 static FORCEINLINE void tmr_smem_intr_clr(uint32_t addr, uint32_t val)
1693 {
1694  WR_WORD(addr, val);
1695 }
1696 
1697 static FORCEINLINE void tmr_smem_intr_mask(uint32_t val)
1698 {
1699  WR_WORD(TIMERS_REGS_SHM_IF_INTR_MASK_SET, val);
1700 }
1701 
1702 static FORCEINLINE void tmr_smem_intr_unmask(uint32_t val)
1703 {
1704  WR_WORD(TIMERS_REGS_SHM_IF_INTR_MASK_CLEAR, val);
1705 }
1706 
1707 static FORCEINLINE uint32_t tmr_smem_cap_data_ready(uint32_t addr)
1708 {
1709  return ((RD_WORD(addr)&TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_DATA_RDY) ? 1 : 0);
1710 }
1711 static FORCEINLINE uint32_t tmr_smem_cap_data_num(uint32_t addr)
1712 {
1713  uint32_t reg = RD_WORD(addr);
1714  uint32_t smem = (reg & TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_SHM)>>TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_SHM_SHIFT;
1715  uint32_t reg_fifo = (reg & TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_REG_FIFO)>>TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_REG_FIFO_SHIFT;
1716  uint32_t fifo = (reg & TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_FIFO)>>TIMERS_REGS_CAP_SHM_NUM_VAL_STS_CAP_SHM_IF_NUM_DATA_IN_FIFO_SHIFT;
1717  return smem + reg_fifo + fifo;
1718 }
1719 static FORCEINLINE uint32_t tmr_smem_cap_data(uint32_t addr)
1720 {
1721  return RD_WORD(addr);
1722 }
1723 
1724 
1725 /*
1726  * Functions
1727  ****************************************************************************************
1728  */
1729 
1738 int hal_timer_busy(void);
1739 
1740 
1755 int hal_timer_set_tmo_callback(int tmr_id, int prio, void *arg, void (*tmr_cb)(void *));
1756 
1757 
1774 int hal_timer_start(int tmr_id, int reload, int manual, uint32_t tick);
1775 
1776 
1787 int hal_timer_stop(int tim_id);
1788 
1789 
1800 int hal_timer_start_tick(int tim_id);
1801 
1814 uint32_t hal_timer_get_tick(int tim_id);
1815 uint32_t hal_timer_get_tick_us(int tim_id);
1816 //float hal_timer_get_tick_us(int tim_id);
1817 
1828 int hal_timer_end_tick(int tim_id);
1829 
1830 
1842 int hal_timer_delay_us(int tim_id, uint32_t usec);
1843 
1851 uint32_t hal_timer_get_systick(void);
1852 
1853 uint32_t hal_timer_us_to_tick(int tmr_id, uint32_t us);
1854 
1855 
1856 int hal_timer_capture_set_callback(int tmr_id, int prio, void *arg, void (*callback)(void *, int, uint32_t));
1857 
1877 int hal_timer_capture_signal_add(int tmr_id, int idx, uint8_t sig_id, int rise, int fall);
1878 
1879 
1891 int hal_timer_capture_signal_rem(int tmr_id, int idx);
1892 
1893 
1894 int hal_timer_smem_capture_set_callback(int prio, void *arg, void (*callback)(void *parg, uint32_t sts, uint32_t cap_num));
1895 int hal_timer_smem_capture_signal_add(int tmr_id, uint8_t sig_id, int rise, int fall, uint16_t max_num, uint16_t full_threshold);
1896 int hal_timer_smem_capture_signal_rem(int tmr_id);
1897 int hal_timer_smem_capture_data_read(int tmr_id, uint32_t *buffer, int len);
1898 uint32_t hal_timer_smem_capture_get_data_num(int tmr_id);
1899 
1900 
1915 int hal_timer_emit_set_callback(int tmr_id, int prio, void *arg, void (*callback)(void *parg,int emit_idx));
1916 
1917 
1933 int hal_timer_emit_add(int tmr_id, int idx, uint32_t tick, tmr_emit_option_t *option);
1934 
1935 
1936 
1947 int hal_timer_emit_rem(int tmr_id, int idx);
1948 
1949 
1950 int hal_timer_smem_emit_set_callback(int tmr_id, int prio, void *arg, void (*callback)(void *parg, uint32_t sts));
1951 
1970 int hal_timer_smem_emit_add(int tmr_id, uint32_t *ticks, uint32_t size, uint16_t empty_threshold, tmr_emit_option_t *option);
1971 
1972 int hal_timer_smem_emit_rem(int tmr_id);
1973 
1974 uint32_t hal_timer_smem_emit_update_tick(int tmr_id, uint32_t *tick_buf, uint32_t buf_len);
1975 
1990 int hal_aon_timer_open(int id, int wup_en, int reload, int prio, void *arg, void (*isr_cb)(void *arg));
1991 
2001 int hal_aon_timer_close(int id);
2002 
2003 
2016 int hal_aon_timer_start(int id, uint64_t time_us);
2017 
2018 
2028 int hal_aon_timer_stop(int id) ;
2029 
2039 uint64_t hal_aon_timer_get_tick(int id);
2040 
2050 uint64_t hal_aon_timer_get_time(int id);
2051 
2052 #if CFG_PM_EN
2053 
2060 void hal_aon_timer_resume(void);
2061 #endif
2062 #if !CFG_PM_EN
2063 
2078 int hal_aon_timer_emit_add(int emit_id, int auto_clr, int touch_clr, uint32_t time_us, int prio, void *arg, void (*callback)(void *));
2079 
2089 int hal_aon_timer_emit_rem(int emit_id);
2090 
2106 int hal_aon_timer_capture_add(int cap_id, uint8_t sig_id, int rise, int fall, int prio, void *arg, void (*callback)(void *, int, uint32_t));
2107 
2108 
2118 int hal_aon_timer_capture_rem(int cap_id);
2119 
2120 #endif
2121 
2123 
2124 #endif // HAL_TIMER_H
tmr_err
tmr_err
(Aon) Timer error code
Definition: hal_timer.h:153
hal_aon_timer_start
int hal_aon_timer_start(int id, uint64_t time_us)
Start sleep timer.
emit_id
emit_id
Timer Emit Id.
Definition: hal_timer.h:70
hal_aon_timer_stop
int hal_aon_timer_stop(int id)
Stop sleep timer.
hal_timer_start_tick
int hal_timer_start_tick(int tim_id)
start timer profile function
hal_timer_emit_add
int hal_timer_emit_add(int tmr_id, int idx, uint32_t tick, tmr_emit_option_t *option)
Add HW trigger to the timer&#39;s trigger list.
hal_timer_smem_emit_add
int hal_timer_smem_emit_add(int tmr_id, uint32_t *ticks, uint32_t size, uint16_t empty_threshold, tmr_emit_option_t *option)
Add HW trigger to the timer&#39;s trigger list.
hal_timer_get_systick
uint32_t hal_timer_get_systick(void)
Return the OS tick.
cap_id
cap_id
Timer Signal Capture Id.
Definition: hal_timer.h:61
hal_timer_emit_rem
int hal_timer_emit_rem(int tmr_id, int idx)
Remove HW trigger from the timer&#39;s trigger list.
hal_timer_end_tick
int hal_timer_end_tick(int tim_id)
timer tick stop function.
tmr_id
tmr_id
Timer Id.
Definition: hal_timer.h:46
hal_timer_busy
int hal_timer_busy(void)
Check if any timer is active.
hal_timer_emit_set_callback
int hal_timer_emit_set_callback(int tmr_id, int prio, void *arg, void(*callback)(void *parg, int emit_idx))
Set emit IRQ handler callback for the timer&#39;s emit.
hal_aon_timer_open
int hal_aon_timer_open(int id, int wup_en, int reload, int prio, void *arg, void(*isr_cb)(void *arg))
Open sleep timer.
hal_timer_get_tick
uint32_t hal_timer_get_tick(int tim_id)
timer get current tick function.
hal_timer_capture_signal_rem
int hal_timer_capture_signal_rem(int tmr_id, int idx)
Remove HW signal from the timer&#39;s capture list.
hal_timer_capture_signal_add
int hal_timer_capture_signal_add(int tmr_id, int idx, uint8_t sig_id, int rise, int fall)
Add HW signal to the timer&#39;s capture list.
hal_aon_timer_emit_rem
int hal_aon_timer_emit_rem(int emit_id)
Remove HW trigger from the AON timer2&#39;s trigger list.
hal_aon_timer_get_time
uint64_t hal_aon_timer_get_time(int id)
Get the current sleep timer time in microsecond.
hal_timer_set_tmo_callback
int hal_timer_set_tmo_callback(int tmr_id, int prio, void *arg, void(*tmr_cb)(void *))
rigster Timer timeout callback function
hal_timer_delay_us
int hal_timer_delay_us(int tim_id, uint32_t usec)
timer delaye function
hal_aon_timer_get_tick
uint64_t hal_aon_timer_get_tick(int id)
Get the current sleep timer tick.
hal_aon_timer_emit_add
int hal_aon_timer_emit_add(int emit_id, int auto_clr, int touch_clr, uint32_t time_us, int prio, void *arg, void(*callback)(void *))
Add HW trigger to the AON timer2&#39;s trigger list.
hal_aon_timer_capture_add
int hal_aon_timer_capture_add(int cap_id, uint8_t sig_id, int rise, int fall, int prio, void *arg, void(*callback)(void *, int, uint32_t))
Add HW trigger to the AON timer2&#39;s trigger list.
hal_aon_timer_close
int hal_aon_timer_close(int id)
Close sleep timer.
hal_timer_start
int hal_timer_start(int tmr_id, int reload, int manual, uint32_t tick)
Run Timer periodic function.
hal_aon_timer_capture_rem
int hal_aon_timer_capture_rem(int cap_id)
Remove HW trigger from the AON timer2&#39;s trigger list.
hal_timer_stop
int hal_timer_stop(int tim_id)
Stop Timer periodic function.