hal_qdec.h

#ifndef HAL_QDEC_H
#define HAL_QDEC_H
#include <stdint.h>
#include "cmsis_os.h"
#include "./hal/hal_power.h"

typedef enum {
    QDEC0_ID = 0, 
    QDEC1_ID, 
    QDEC2_ID, 
    QDEC_MAX_ID, 
} qdec_id_t;

enum qdec_error {
    QDEC_ERR_OK = 0,
    QDEC_ERR_INVALID_PARAM = -1,
    QDEC_ERR_PINMUX = -2,
    QDEC_ERR_BUSY = -3,
    QDEC_ERR_MUTEX = -4,
};



typedef struct qdec_init {
    uint16_t report_intvl; 
    uint16_t sample_intvl; 
    int move_dir; 
    int  prio; 
    void* arg; 
    void(*callback)(void*, int, uint32_t, int); 
} qdec_init_t;
typedef struct qdec_cfg {
    int8_t a_port; 
    int8_t a_pin;  
    int8_t b_port; 
    int8_t b_pin;  
    int8_t debounce; 
    int8_t idx_en;  
    int8_t idx_port;  
    int8_t idx_pin;     
    int8_t idx_pol; 
    int8_t led_en;  
    int8_t led_pol; 
    uint16_t led_on_time; 
} qdec_cfg_t;
typedef struct qdec_idx_cfg {
    int8_t rst_en; 
    uint8_t pattern_len; 
    uint8_t pattern[4]; 
} qdec_idx_cfg_t;

static INLINE uint32_t qdec_intr_status(void)
{
    return RD_WORD(QUADDEC_REG_INTERRUPT_STATUS);
}
static INLINE uint32_t qdec_intr_mask_status(void)
{
    return RD_WORD(QUADDEC_REG_INTERRUPT_MASK_STATUS);
}

static INLINE void qdec_intr_clear(uint32_t val)
{
    WR_WORD(QUADDEC_REG_INTERRUPT_CLEAR, val);
}
static INLINE void qdec_intr_set(uint32_t val)
{
    WR_WORD(QUADDEC_REG_INTERRUPT_SET, val);
}
static INLINE void qdec_intr_mask_clear(uint32_t val)
{
    WR_WORD(QUADDEC_REG_INTERRUPT_MASK_CLEAR, val);
}
static INLINE void qdec_intr_mask_set(uint32_t val)
{
    WR_WORD(QUADDEC_REG_INTERRUPT_MASK_SET, val);
}



/*
 *        intval = led<<16 | smaple. 
 *              sample: actual sample interval = (register value + 64) * 2 us
 *              led:     actual early start interval = register value * 1 us.
 *              Register value 0 is invalid. If this field has an effectively longer time than sample_interval field, the LED will always be asserted.
 * */
static INLINE void qdec_sample_interval(uint16_t intv)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_INTERVAL_SETTING);
    reg &= ~QUADDEC_REG_INTERVAL_SETTING_CTL_SAMPLE_INTERVAL_M1;
    reg |= intv;
    WR_WORD(QUADDEC_REG_INTERVAL_SETTING,reg);
}

//How many samples the counter value in the register will be updated (and an counter ready interrupt triggered). 
//If value is 0, the counter will be updated every sample. Max value is 0xff
static INLINE void qdec_report_interval(uint32_t intv)
{
    WR_WORD(QUADDEC_REG_REPORT_INTERVAL,intv);
}

//Actual led on = register value * 1 us. 
static INLINE void qdec_led_inertval(uint8_t id, uint32_t intv)
{
    WR_WORD(QUADDEC_REG_INTERVAL_LED_SETTING_M0 + id*4,intv);
}

static INLINE void qdec_counter_lmt(uint32_t lmt)
{

    WR_WORD(QUADDEC_REG_COUNTER_LMT,lmt);
}

static INLINE void qdec_counter_init(uint32_t init)
{
    WR_WORD(QUADDEC_REG_COUNTER_INIT,init);
}

static INLINE void qdec_counter_clear(uint32_t val)
{
    WR_WORD(QUADDEC_REG_COUNTER_CLEAR,val);
}

//current sample counter value
static INLINE uint32_t qdec_curr_sample(int id)
{
    return RD_WORD(QUADDEC_REG_SAMPLE_COUNTER0 + id*4)&0xff;
}

//sample counter value from last report time 
static INLINE uint32_t qdec_report_sample(int id)
{
    return (RD_WORD(QUADDEC_REG_SAMPLE_COUNTER0 + id*4)>>16)&0xff;
}

static INLINE uint32_t qdec_get_db_counter(int id)
{
    return RD_WORD(QUADDEC_REG_DB_COUNTER_AND_CURRENT_INPUT0 + id*4);
}

static INLINE void qdec_idx_ctrl(uint32_t val)
{
    WR_WORD(QUADDEC_REG_INDEX_CTRL, val);
} 

static INLINE uint32_t qdec_get_index_counter(int id)
{
    return RD_WORD(QUADDEC_REG_INDEX_COUNTER0 + id*4);
}
#if 0
static INLINE uint32_t qdec_get_misc_ctrl(void)
{
    return RD_WORD(QUADDEC_REG_MISC_CTRL);
}

static INLINE void qdec_set_misc_ctrl(uint32_t misc)
{
    WR_WORD(QUADDEC_REG_MISC_CTRL, misc);
}
#endif
static INLINE void qdec_set_pin_a(int id, uint32_t a)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4);
    reg &= ~QUADDEC_REG_INPUT_PIN_ASSIGNMENT0_CTL_PIN_A_SEL0;
    reg |= a&0x3;
    WR_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4, reg);
}
static INLINE void qdec_set_pin_b(int id, uint32_t b)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4);
    reg &= ~QUADDEC_REG_INPUT_PIN_ASSIGNMENT0_CTL_PIN_B_SEL0;
    reg |= (b&0x3)<<4;
    WR_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4, reg);
}
static INLINE void qdec_set_pin_idx(int id, uint32_t idx)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4);
    reg &= ~QUADDEC_REG_INPUT_PIN_ASSIGNMENT0_CTL_PIN_IDX_SEL0;
    reg |= (idx&0x3)<<8;
    WR_WORD(QUADDEC_REG_INPUT_PIN_ASSIGNMENT0 + id*4, reg);
}



static INLINE void qdec_enable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg |= 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_QUADDEC_ENABLE_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_disable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    uint32_t mask = 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_QUADDEC_ENABLE_SHIFT);
    reg &= ~mask;
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_led_enable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg |= 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_LED_EN_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_led_disable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    uint32_t mask = 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_LED_EN_SHIFT);
    reg &= ~mask;
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_led_pol(int id, uint8_t pol)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg &= ~(0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_LED_POLARITY_SHIFT));
    reg |= (pol&0x1UL)<<(id+QUADDEC_REG_MISC_CTRL_CTL_LED_POLARITY_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
}
static INLINE void qdec_idx_enable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg |= 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_INDEX_EN_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_idx_disable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    uint32_t mask = 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_INDEX_EN_SHIFT);
    reg &= ~mask;
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_idx_pol(int id, uint8_t pol)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg &= ~(0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_INDEX_POLARITY_SHIFT));
    reg |= (pol&0x1UL)<<(id+QUADDEC_REG_MISC_CTRL_CTL_INDEX_POLARITY_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
}
static INLINE void qdec_debounce_enable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    reg |= 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_DEBOUNCE_EN_SHIFT);
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_debounce_disable(int id)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    id &= 0x3;
    uint32_t mask = 0x1UL<<(id+QUADDEC_REG_MISC_CTRL_CTL_DEBOUNCE_EN_SHIFT);
    reg &= ~mask;
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}
static INLINE void qdec_clk_num_in_us(uint8_t num)
{
    uint32_t reg = RD_WORD(QUADDEC_REG_MISC_CTRL);
    reg &= ~QUADDEC_REG_MISC_CTRL_CTL_NUM_CLK_IN_US_M1;
    reg |= (num&QUADDEC_REG_MISC_CTRL_CTL_NUM_CLK_IN_US_M1_MASK)<<QUADDEC_REG_MISC_CTRL_CTL_NUM_CLK_IN_US_M1_SHIFT;
    WR_WORD(QUADDEC_REG_MISC_CTRL, reg);
    
}



int hal_qdec_open(qdec_init_t *init);


int hal_qdec_cfg(int id, qdec_cfg_t *cfg);


int hal_qdec_idx_cfg(qdec_idx_cfg_t *cfg);


int hal_qdec_enable(int id);



int hal_qdec_disable(int id);

void hal_qdec_close(void);


#endif