hal_i2s.h

#ifndef HAL_I2S_H
#define HAL_I2S_H

#include "stdint.h"
#include "in_mmap.h"
#include "in_compile.h"
/*
 * Defines
 ****************************************************************************************
 */
 
#define I2S_CH0_BASE_OFS    (0x20)
#define I2S_CH1_BASE_OFS    (0x60)
 
#define MI2S_CH0_BASE       (I2S_MASTER_BASE + I2S_CH0_BASE_OFS)
#define MI2S_CH1_BASE       (I2S_MASTER_BASE + I2S_CH1_BASE_OFS)

#define SI2S_CH0_BASE       (I2S_SLAVE_BASE + I2S_CH0_BASE_OFS)
#define SI2S_CH1_BASE       (I2S_SLAVE_BASE + I2S_CH1_BASE_OFS)

#define I2S_REG_IER_OFS     0x00000000UL
#define I2S_REG_IRER_OFS        0x00000004UL
#define I2S_REG_ITER_OFS        0x00000008UL
#define I2S_REG_CER_OFS     0x0000000CUL
#define I2S_REG_CCR_OFS     0x00000010UL
#define I2S_REG_RXFFR_OFS   0x00000014UL
#define I2S_REG_TXFFR_OFS   0x00000018UL
#define I2S_REG_LRBR_OFS    0x00000000UL
#define I2S_REG_LTHR_OFS        0x00000000UL
#define I2S_REG_RRBR_OFS    0x00000004UL
#define I2S_REG_RTHR_OFS    0x00000004UL
#define I2S_REG_RER_OFS     0x00000008UL
#define I2S_REG_TER_OFS     0x0000000CUL
#define I2S_REG_RCR_OFS     0x00000010UL
#define I2S_REG_TCR_OFS     0x00000014UL
#define I2S_REG_ISR_OFS     0x00000018UL
#define I2S_REG_IMR_OFS     0x0000001CUL
#define I2S_REG_ROR_OFS     0x00000020UL
#define I2S_REG_TOR_OFS     0x00000024UL
#define I2S_REG_RFCR_OFS    0x00000028UL
#define I2S_REG_TFCR_OFS        0x0000002CUL
#define I2S_REG_RFF_OFS     0x00000030UL
#define I2S_REG_TFF_OFS     0x00000034UL
#define I2S_REG_RXDMA_OFS   0x000001C0UL
#define I2S_REG_RRXDMA_OFS  0x000001C4UL
#define I2S_REG_TXDMA_OFS   0x000001C8UL
#define I2S_REG_RTXDMA_OFS  0x000001CCUL

/*
 * Enumerations
 ****************************************************************************************
 */

enum i2s_id {
    MI2S_ID = 1,
    SI2S_ID = 2,
};

enum i2s_word_size {
    I2S_WS_16BITS = 16,
    I2S_WS_24BITS = 24,
    I2S_WS_32BITS = 32
};

enum i2s_sr {
    I2S_SR_8K = 8000,
    I2S_SR_16K = 16000,
    I2S_SR_24K = 24000,
    I2S_SR_32K = 32000,
    I2S_SR_36K = 36000,
    I2S_SR_44K = 44100,
    I2S_SR_48K = 48000,
};

enum i2s_type {
    I2S_MONO = 1,
    I2S_STEREO,
};

enum i2s_ch_id {
    I2S_CH_1,
    I2S_CH_2,
    I2S_CH_MAX,
};

enum i2s_ch_dir {
    I2S_DIR_TX = 1,
    I2S_DIR_RX = 2,
};

enum i2s_ch_word_sz {
    I2S_CH_WS_0_BIT = 0,
    I2S_CH_WS_12_BITS,
    I2S_CH_WS_16_BITS,
    I2S_CH_WS_20_BITS,
    I2S_CH_WS_24_BITS,
    I2S_CH_WS_32_BITS,
};

enum i2s_error {
    I2S_ERR_OK = 0,
    I2S_ERR_INVALID_PARAM = -1,
    I2S_ERR_INVALID_STATE = -2,
    I2S_ERR_RX_OV = -4,
    I2S_ERR_TX_OV = -5,
    I2S_ERR_DMA_NOT_AVAIL = -6,
    I2S_ERR_DMA_TRAN = -7,
} ;

/*
 * Inline Functions
 ****************************************************************************************
 */

static INLINE void i2s_enable(uint32_t base)
{
    WR_WORD((base + I2S_REG_IER_OFS), 1);
}

static INLINE void i2s_disable(uint32_t base)
{
    WR_WORD((base + I2S_REG_IER_OFS), 0);
}

static INLINE void i2s_rx_enable(uint32_t base)
{
    WR_WORD((base + I2S_REG_IRER_OFS), 1);
}

static INLINE void i2s_rx_disable(uint32_t base)
{
    WR_WORD((base + I2S_REG_IRER_OFS), 0);
}

static INLINE void i2s_tx_enable(uint32_t base)
{
    WR_WORD((base + I2S_REG_ITER_OFS), 1);
}

static INLINE void i2s_tx_disable(uint32_t base)
{
    WR_WORD((base + I2S_REG_ITER_OFS), 0);
}

static INLINE void i2s_sclk_enable(uint32_t base)
{
    WR_WORD((base + I2S_REG_CER_OFS), 1);
}

static INLINE void i2s_sclk_disable(uint32_t base)
{
    WR_WORD((base + I2S_REG_CER_OFS), 0);
}

#define I2S_CCR_SCLKG       0x00000007UL
#define I2S_CCR_WSS         0x00000018UL

#define I2S_CCR_SCLKG_NG    0
#define I2S_CCR_SCLKG_12        1
#define I2S_CCR_SCLKG_16        2
#define I2S_CCR_SCLKG_20        3
#define I2S_CCR_SCLKG_24        4

#define I2S_CCR_WSS_16      0
#define I2S_CCR_WSS_24      1
#define I2S_CCR_WSS_32      2
static INLINE void i2s_sclk_wss(uint32_t base, int wss)
{
    uint32_t reg = RD_WORD(base + I2S_REG_CCR_OFS);
    
    reg &= ~I2S_CCR_WSS;
    reg |= ((wss & 0x3) << 3);

    WR_WORD((base + I2S_REG_CCR_OFS), reg);
}

static INLINE void i2s_sclk_gate(uint32_t base, int gated_clk)
{
    uint32_t reg = RD_WORD(base + I2S_REG_CCR_OFS);
    
    reg &= ~I2S_CCR_SCLKG;
    reg |= (gated_clk & 0x7);

    WR_WORD((base + I2S_REG_CCR_OFS), reg);
}

static INLINE void i2s_rx_fifo_reset(uint32_t base)
{
    WR_WORD((base + I2S_REG_RXFFR_OFS), 1);
}

static INLINE void i2s_tx_fifo_reset(uint32_t base)
{
    WR_WORD((base + I2S_REG_TXFFR_OFS), 1);
}

static INLINE uint32_t i2s_chx_lrx_data(uint32_t ch_base)
{
    return RD_WORD(ch_base + I2S_REG_LRBR_OFS);
}

static INLINE void i2s_chx_ltx_data(uint32_t ch_base, uint32_t data)
{
    WR_WORD((ch_base + I2S_REG_LTHR_OFS), data);
}

static INLINE uint32_t i2s_chx_rrx_data(uint32_t ch_base)
{
    return RD_WORD(ch_base + I2S_REG_RRBR_OFS);
}

static INLINE void i2s_chx_rtx_data(uint32_t ch_base, uint32_t data)
{
    WR_WORD((ch_base + I2S_REG_RTHR_OFS), data);
}

static INLINE void i2s_chx_rx_enable(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_RER_OFS), 1);
}

static INLINE void i2s_chx_rx_disable(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_RER_OFS), 0);
}

static INLINE void i2s_chx_tx_enable(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_TER_OFS), 1);
}

static INLINE void i2s_chx_tx_disable(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_TER_OFS), 0);
}

#define I2S_CHx_RCR_WLEN        0x00000007UL

#define I2S_CHx_WLEN_0      0
#define I2S_CHx_WLEN_12     1
#define I2S_CHx_WLEN_16     2
#define I2S_CHx_WLEN_20     3
#define I2S_CHx_WLEN_24     4
#define I2S_CHx_WLEN_32     5

static INLINE void i2s_chx_rx_wlen(uint32_t ch_base, int word_len)
{
    WR_WORD((ch_base + I2S_REG_RCR_OFS), (word_len & 0x7));
}

#define I2S_CHx_TCR_WLEN        0x00000007UL

static INLINE void i2s_chx_tx_wlen(uint32_t ch_base, int word_len)
{
    WR_WORD((ch_base + I2S_REG_TCR_OFS), (word_len & 0x7));
}

#define I2S_CHx_IT_RXDA 0x00000001UL
#define I2S_CHx_IT_RXFO 0x00000002UL
#define I2S_CHx_IT_TXFE     0x00000010UL
#define I2S_CHx_IT_TXFO 0x00000020UL    
#define I2S_CHx_IT_ALL      0x00000033UL    

static INLINE uint32_t i2s_chx_intr_status(uint32_t ch_base)
{
    return (RD_WORD(ch_base + I2S_REG_ISR_OFS));
}

static INLINE void i2s_chx_intr_mask(uint32_t ch_base, uint32_t mask)
{
    uint32_t reg = RD_WORD(ch_base + I2S_REG_IMR_OFS);
    reg |= mask;
    WR_WORD((ch_base + I2S_REG_IMR_OFS), reg); 
}

static INLINE void i2s_chx_intr_unmask(uint32_t ch_base, uint32_t mask)
{
    uint32_t reg = RD_WORD(ch_base + I2S_REG_IMR_OFS);
    reg &= ~mask;
    WR_WORD((ch_base + I2S_REG_IMR_OFS), reg); 
}

static INLINE void i2s_chx_rov_clr(uint32_t ch_base)
{
    RD_WORD(ch_base + I2S_REG_ROR_OFS);
}

static INLINE void i2s_chx_tov_clr(uint32_t ch_base)
{
    RD_WORD(ch_base + I2S_REG_TOR_OFS);
}

#define I2S_CHx_RFCR_RXCHDT     0x0000000FUL
static INLINE void i2s_chx_rfifo_tl(uint32_t ch_base, uint32_t tl)
{
    WR_WORD((ch_base + I2S_REG_RFCR_OFS), (tl & 0xF)); 
}

#define I2S_CHx_TFCR_TXCHDT     0x0000000FUL
static INLINE void i2s_chx_tfifo_tl(uint32_t ch_base, uint32_t tl)
{
    WR_WORD((ch_base + I2S_REG_TFCR_OFS), (tl & 0xF)); 
}

static INLINE void i2s_chx_rfifo_flush(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_RFF_OFS), 1); 
}

static INLINE void i2s_chx_tfifo_flush(uint32_t ch_base)
{
    WR_WORD((ch_base + I2S_REG_TFF_OFS), 1); 
}

static INLINE void i2s_sd_oe(int id, int ch_id, int oe)
{
    uint32_t reg = RD_WORD(GLOBAL_REG_I2S_OEN_CTRL);
    if (id == MI2S_ID) {
        if (ch_id == I2S_CH_1) {
            if (oe) {
                reg &= ~GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_MASTER_PIN0_OEN;
            } else {
                reg |= GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_MASTER_PIN0_OEN;
            }
        } else {
            if (oe) {
                reg &= ~GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_MASTER_PIN1_OEN;
            } else {
                reg |= GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_MASTER_PIN1_OEN;
            }
        }
    } else {
        if (ch_id == I2S_CH_1) {
            if (oe) {
                reg &= ~GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_SLAVE_SD_OEN;
            } else {
                reg |= GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_SLAVE_SD_OEN;
            }
        } else {
            if (oe) {
                reg &= ~GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_SLAVE_SD_BKUP_OEN;
            } else {
                reg |= GLOBAL_REG_I2S_OEN_CTRL_CTL_I2S_SLAVE_SD_BKUP_OEN;
            }
        }
    }
    WR_WORD(GLOBAL_REG_I2S_OEN_CTRL, reg); 
}

static INLINE void i2s_txdma_start(uint32_t base)
{
    WR_WORD((base + I2S_REG_TXDMA_OFS), 0);
}

/*
 * APIs 
 ****************************************************************************************
 */

void *hal_i2s_open(int id, int sr, int word_sz);

int hal_i2s_close(void *hdl) ;

int hal_i2s_ch_en(void *hdl, int ch_id, int dir, int ch_word_sz, void *buffer0, void *buffer1, uint16_t buffer_len, void *arg, void (*callback)(void * arg, int id, int status) );

int hal_i2s_ch_dis(void *hdl, int ch_id, int dir);


#endif