hal_hwacc.h

#ifndef HAL_HWACC_H
#define HAL_HWACC_H

#include <stdint.h>
#include <math.h>
#include "in_mmap.h"
#include "in_config.h"

/*
 ****************************************************************************************
 * INLINE FUNCTIONS
 ****************************************************************************************
 */
 
static __inline uint8_t hwacc_get_intr_status()
{
    return RD_WORD(HWACC_REG_INTR_STATUS);
}
 
static __inline uint8_t hwacc_get_mask_status()
{
    return RD_WORD(HWACC_REG_INTR_MASK_STATUS);
}

static __inline void hwacc_intr_clear()
{
    WR_WORD(HWACC_REG_INTR_CLEAR, (HWACC_REG_INTR_CLEAR_HWACC_DONE | HWACC_REG_INTR_CLEAR_FAULT_DETECTED));
}

static __inline void hwacc_intr_set()
{
    WR_WORD(HWACC_REG_INTR_SET, (HWACC_REG_INTR_SET_HWACC_DONE | HWACC_REG_INTR_SET_FAULT_DETECTED));
}

static __inline void hwacc_mask_clear()
{
    WR_WORD(HWACC_REG_INTR_MASK_CLEAR, (HWACC_REG_INTR_MASK_CLEAR_HWACC_DONE | HWACC_REG_INTR_MASK_CLEAR_FAULT_DETECTED));
}

static __inline void hwacc_mask_set()
{
    WR_WORD(HWACC_REG_INTR_MASK_SET, (HWACC_REG_INTR_MASK_SET_HWACC_DONE | HWACC_REG_INTR_MASK_SET_FAULT_DETECTED));
}

static __inline void hwacc_enable()
{
    uint32_t reg = RD_WORD(HWACC_REG_MISC_CTRL);
    reg |= HWACC_REG_MISC_CTRL_CTL_ENABLE;
    WR_WORD(HWACC_REG_MISC_CTRL, reg);
}

static __inline void hwacc_disable()
{
    uint32_t reg = RD_WORD(HWACC_REG_MISC_CTRL);
    reg &= ~HWACC_REG_MISC_CTRL_CTL_ENABLE;
    WR_WORD(HWACC_REG_MISC_CTRL, reg);
}

static __inline void hwacc_start()
{
    uint32_t reg = RD_WORD(HWACC_REG_MISC_CTRL);
    reg |= HWACC_REG_MISC_CTRL_CTL_START;
    WR_WORD(HWACC_REG_MISC_CTRL, reg);

    reg &= ~HWACC_REG_MISC_CTRL_CTL_START;
    WR_WORD(HWACC_REG_MISC_CTRL, reg);
}

static __inline void hwacc_set_num_inst(uint16_t num_inst)
{
    uint32_t reg = RD_WORD(HWACC_REG_MISC_CTRL);
    reg &= ~HWACC_REG_MISC_CTRL_CTL_NUM_INSTRUCTION;
    reg |= ((num_inst & HWACC_REG_MISC_CTRL_CTL_NUM_INSTRUCTION_MASK) << HWACC_REG_MISC_CTRL_CTL_NUM_INSTRUCTION_SHIFT);
    WR_WORD(HWACC_REG_MISC_CTRL, reg);
}

static __inline void hwacc_set_inst_addr(uint16_t inst_addr)
{
    uint32_t reg = RD_WORD(HWACC_REG_MISC_CTRL);
    reg &= ~HWACC_REG_MISC_CTRL_CTL_INSTRUCTION_ADDRESS;
    reg |= ((inst_addr & HWACC_REG_MISC_CTRL_CTL_INSTRUCTION_ADDRESS_MASK) << HWACC_REG_MISC_CTRL_CTL_INSTRUCTION_ADDRESS_SHIFT);
    WR_WORD(HWACC_REG_MISC_CTRL, reg);
}

static __inline void hwacc_mem_acc_ahb()
{
    WR_WORD(HWACC_REG_MEM_ACC_CTRL, HWACC_REG_MEM_ACC_CTRL_DEFAULT);
}

static __inline void hwacc_mem_acc_comp_core()
{
    WR_WORD(HWACC_REG_MEM_ACC_CTRL, HWACC_REG_MEM_ACC_CTRL_CTL_MEM_A_ACC_SEL | HWACC_REG_MEM_ACC_CTRL_CTL_MEM_B_ACC_SEL | HWACC_REG_MEM_ACC_CTRL_CTL_MEM_C_ACC_SEL | HWACC_REG_MEM_ACC_CTRL_CTL_MEM_D_ACC_SEL);
}

static __inline void hwacc_pv_search_enable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg |= HWACC_REG_INVERSE_CTRL_CTL_PV_SEARCH_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_pv_search_disable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg &= ~HWACC_REG_INVERSE_CTRL_CTL_PV_SEARCH_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_check_min_pv_enable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg |= HWACC_REG_INVERSE_CTRL_CTL_CHECK_MIN_PV_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_check_min_pv_disable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg &= ~HWACC_REG_INVERSE_CTRL_CTL_CHECK_MIN_PV_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_check_zero_pv_enable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg |= HWACC_REG_INVERSE_CTRL_CTL_CHECK_ZERO_PV_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_check_zero_pv_disable()
{
    uint32_t reg = RD_WORD(HWACC_REG_INVERSE_CTRL);
    reg &= ~HWACC_REG_INVERSE_CTRL_CTL_CHECK_ZERO_PV_ON;
    WR_WORD(HWACC_REG_INVERSE_CTRL, reg);
}

static __inline void hwacc_set_min_pv(uint32_t min_pv)
{
    WR_WORD(HWACC_REG_INVERSE_MIN_PV, min_pv);
}
 
static __inline uint32_t hwacc_get_curr_inst_word_0()
{
    return RD_WORD(HWACC_REG_CURR_INST_WORD0);
}
 
static __inline uint32_t hwacc_get_curr_inst_word_1()
{
    return RD_WORD(HWACC_REG_CURR_INST_WORD1);
}
 
static __inline uint32_t hwacc_get_curr_inst_word_2()
{
    return RD_WORD(HWACC_REG_CURR_INST_WORD2);
}
 
static __inline uint32_t hwacc_get_curr_inst_cycle_cnt()
{
    return RD_WORD(HWACC_REG_CURR_INST_CYCLE_CNT);
}

/*
 ****************************************************************************************
 * IMPLEMENTATION
 ****************************************************************************************
 */

#define HWACC_MEM_0_BASE_ADDR       0x44007000
#define HWACC_MEM_1_BASE_ADDR       0x44007800
#define HWACC_MEM_2_BASE_ADDR       0x44008000
#define HWACC_MEM_3_BASE_ADDR       0x44008400

typedef enum {  
    HWACC_OP_COPY = 0,
    HWACC_OP_ADD = 1,
    HWACC_OP_SUB = 2,
    HWACC_OP_MUL = 3,
    HWACC_OP_INV = 4,
    HWACC_OP_EQU = 5,
    HWACC_OP_CLEAR = 6,
    HWACC_OP_SCALE = 7,
} hwacc_op_t;

typedef struct {
    uint8_t mem_block;
    uint16_t offset;
    uint8_t nrows;
    uint8_t ncols;
} hwacc_matrix_desc_t;

typedef enum {
    HWACC_ERR_OK = 0,
    HWACC_ERR_CONFIG_ERROR = 1,
    HWACC_ERR_INST_OVERFLOW = 2, 
    HWACC_ERR_ALREADY_INIT = 3,
    HWACC_ERR_NOT_INIT = 4,
    HWACC_ERR_BAD_STATE = 5,
    HWACC_ERR_DIMENSION_MISMATCH = 6,
    HWACC_ERR_BAD_INPUT = 7,
} hwacc_status_t;

// DEFAULT INITIALIZATION
int hal_hwacc_open(void);

int hal_hwacc_close(void);

int hal_hwacc_write_matrix(hwacc_matrix_desc_t *matrix, const float *head);

int hal_hwacc_read_matrix(hwacc_matrix_desc_t *matrix, float *head);

int hal_hwacc_insert_inst(hwacc_matrix_desc_t *matrix_C, int C_symm, hwacc_matrix_desc_t *matrix_A, int A_trans, hwacc_matrix_desc_t *matrix_B, int B_trans, hwacc_op_t op);

int hal_hwacc_execute(void);

#endif