InPlay API
hal_dma.h
1 
13 #ifndef HAL_DMA_H
14 #define HAL_DMA_H
15 
25 #include "in_mmap.h"
26 
27 /*
28  * Defines
29  ****************************************************************************************
30  */
31 
32 #define DMA_REG_CFG_OFS 0x00000398UL
33 #define DMA_REG_CH_EN_OFS 0x000003A0UL
34 
35 #define DMA_REG_INTR_RAW_TFR 0x000002C0UL
36 #define DMA_REG_INTR_RAW_BLOCK 0x000002C8UL
37 #define DMA_REG_INTR_RAW_SRC 0x000002D0UL
38 #define DMA_REG_INTR_RAW_DST 0x000002D8UL
39 #define DMA_REG_INTR_RAW_ERR 0x000002E0UL
40 
41 #define DMA_REG_INTR_STAT_TFR 0x000002E8UL
42 #define DMA_REG_INTR_STAT_BLOCK 0x000002F0UL
43 #define DMA_REG_INTR_STAT_SRC 0x000002F8UL
44 #define DMA_REG_INTR_STAT_DST 0x00000300UL
45 #define DMA_REG_INTR_STAT_ERR 0x00000308UL
46 
47 #define DMA_REG_INTR_MASK_TFR 0x00000310UL
48 #define DMA_REG_INTR_MASK_BLOCK 0x00000318UL
49 #define DMA_REG_INTR_MASK_SRC 0x00000320UL
50 #define DMA_REG_INTR_MASK_DST 0x00000328UL
51 #define DMA_REG_INTR_MASK_ERR 0x00000330UL
52 
53 #define DMA_REG_INTR_CLR_TFR 0x00000338UL
54 #define DMA_REG_INTR_CLR_BLOCK 0x00000340UL
55 #define DMA_REG_INTR_CLR_SRC 0x00000348UL
56 #define DMA_REG_INTR_CLR_DST 0x00000350UL
57 #define DMA_REG_INTR_CLR_ERR 0x00000358UL
58 
59 #define DMA_REG_INTR_STAT 0x00000360UL
60 
61 #define DMA_REG_SRC_SW_REQ 0x00000368UL
62 #define DMA_REG_DST_SW_REQ 0x00000370UL
63 #define DMA_REG_SRC_SW_SGLREQ 0x00000378UL
64 #define DMA_REG_DST_SW_SGLREQ 0x00000380UL
65 #define DMA_REG_LST_SRC_SW_REQ 0x00000388UL
66 #define DMA_REG_LST_DST_SW_REQ 0x00000390UL
67 
68 #define DMA_CH_REG_SAR_OFS 0x00000000UL
69 #define DMA_CH_REG_DAR_OFS 0x00000008UL
70 #define DMA_CH_REG_LLP_OFS 0x00000010UL
71 #define DMA_CH_REG_CTL_OFS 0x00000018UL
72 #define DMA_CH_REG_SSTAT_OFS 0x00000020UL
73 #define DMA_CH_REG_DSTAT_OFS 0x00000028UL
74 #define DMA_CH_REG_SSTATAR_OFS 0x00000030UL
75 #define DMA_CH_REG_DSTATAR_OFS 0x00000038UL
76 #define DMA_CH_REG_CFG_OFS 0x00000040UL
77 #define DMA_CH_REG_SGR_OFS 0x00000048UL
78 #define DMA_CH_REG_DSR_OFS 0x00000050UL
79 
80 #define DMA_CH_REG_GAP 0x58
81 #define DMA_MAX_CTL_NB 2
82 #define DMA_MAX_CH_NB 4
83 
84 #define DMA_IT_STATUS_TFR 0x00000001UL
85 #define DMA_IT_STATUS_BLOCK 0x00000002UL
86 #define DMA_IT_STATUS_SRCT 0x00000004UL
87 #define DMA_IT_STATUS_DSTT 0x00000008UL
88 #define DMA_IT_STATUS_ERR 0x00000010UL
89 #define DMA_IT_STATUS_ALL 0x0000001FUL
90 
91 #define DMA_CH_CTL_INT_EN 0x00000001UL
92 #define DMA_CH_CTL_DST_TR_WIDTH 0x0000000EUL
93 #define DMA_CH_CTL_SRC_TR_WIDTH 0x00000070UL
94 #define DMA_CH_CTL_DINC 0x00000180UL
95 #define DMA_CH_CTL_SINC 0x00000600UL
96 #define DMA_CH_CTL_DEST_MSIZE 0x00003800UL
97 #define DMA_CH_CTL_SRC_MSIZE 0x0001C000UL
98 #define DMA_CH_CTL_TT_FC 0x00700000UL
99 #define DMA_CH_CTL_DMS 0x01800000UL
100 #define DMA_CH_CTL_SMS 0x06000000UL
101 #define DMA_CH_CTL_LLP_DST_EN 0x08000000UL
102 #define DMA_CH_CTL_LLP_SRC_EN 0x10000000UL
103 #define DMA_CH_CTL_BLOCK_TS 0x0000FFFFUL
104 
105 #define DMA_CH_CFG_PRIOR 0x000000E0UL
106 #define DMA_CH_CFG_SUSP 0x00000100UL
107 #define DMA_CH_CFG_FIFO_EMPTY 0x00000200UL
108 #define DMA_CH_CFG_HS_SEL_DST 0x00000400UL
109 #define DMA_CH_CFG_HS_SEL_SRC 0x00000800UL
110 #define DMA_CH_CFG_LOCK_CH_L 0x00003000UL
111 #define DMA_CH_CFG_LOCK_B_L 0x0000C000UL
112 #define DMA_CH_CFG_LOCK_CH 0x00010000UL
113 #define DMA_CH_CFG_LOCK_B 0x00020000UL
114 #define DMA_CH_CFG_DST_HS_POL 0x00040000UL
115 #define DMA_CH_CFG_SRC_HS_POL 0x00080000UL
116 #define DMA_CH_CFG_RELOAD_SRC 0x40000000UL
117 #define DMA_CH_CFG_RELOAD_DST 0x80000000UL
118 #define DMA_CH_CFG_FCMODE 0x00000001UL
119 #define DMA_CH_CFG_FIFO_MODE 0x00000002UL
120 #define DMA_CH_CFG_DS_UPD_EN 0x00000020UL
121 #define DMA_CH_CFG_SS_UPD_EN 0x00000040UL
122 #define DMA_CH_CFG_SRC_PER 0x00000780UL
123 #define DMA_CH_CFG_DEST_PER 0x00007800UL
124 
125 /*
126  * Enumeration
127  ****************************************************************************************
128  */
129 
130 enum dma_id {
131  DMA0_ID,
132  DMA1_ID,
133 };
134 
135 enum dma_error_code {
136  DMA_ERR_OK = 0,
137  DMA_ERR_BAD_STATE = -1,
138  DMA_ERR_INVALID_PARA = -2,
139  DMA_ERR_TRAN = -3,
140  DMA_ERR_BLOCK = -4,
141 } ;
142 
143 enum dma0_periph_id {
144  DMA_ID_MSPI0_TX,
145  DMA_ID_MSPI1_TX,
146  DMA_ID_SSPI1_TX,
147  DMA_ID_SSPI0_TX,
148  DMA_ID_I2S_MASTER_TX,
149  DMA_ID_I2S_SLAVE_TX,
150  DMA_ID_I2C0_TX,
151  DMA_ID_I2C1_TX,
152  DMA_ID_UART0_TX,
153  DMA_ID_UART1_TX,
154  DMA_ID_AUD_ENC_TX,
155 };
156 
157 enum dma1_periph_id {
158  DMA_ID_MSPI0_RX,
159  DMA_ID_MSPI1_RX,
160  DMA_ID_SSPI1_RX,
161  DMA_ID_SSPI0_RX,
162  DMA_ID_I2S_MASTER_RX,
163  DMA_ID_I2S_SLAVE_RX,
164  DMA_ID_I2C0_RX,
165  DMA_ID_I2C1_RX,
166  DMA_ID_UART0_RX,
167  DMA_ID_UART1_RX,
168  DMA_ID_AUD_DEC_RX,
169 };
170 
171 enum dma_tr_width {
172  DMA_CTL_TR_WIDTH_8BITS = 0,
173  DMA_CTL_TR_WIDTH_16BITS,
174  DMA_CTL_TR_WIDTH_32BITS,
175  DMA_CTL_TR_WIDTH_64BITS,
176  DMA_CTL_TR_WIDTH_128BITS,
177  DMA_CTL_TR_WIDTH_256BITS,
178 };
179 
180 enum dma_tr_msize {
181  DMA_CTL_TR_MSIZE_1 = 0,
182  DMA_CTL_TR_MSIZE_4,
183  DMA_CTL_TR_MSIZE_8,
184  DMA_CTL_TR_MSIZE_16,
185  DMA_CTL_TR_MSIZE_32,
186  DMA_CTL_TR_MSIZE_64,
187 };
188 
189 enum dma_addr_chg {
190  DMA_ADDR_INC = 0,
191  DMA_ADDR_DEC = 1,
192  DMA_ADDR_SAME = 2,
193 };
194 
195 enum dma_ttype {
196  DMA_TT_MEM_TO_MEM_FC_DMAC = 0,
197  DMA_TT_MEM_TO_PERF_FC_DMAC,
198  DMA_TT_PERF_TO_MEM_FC_DMAC,
199  DMA_TT_PERF_TO_PERF_FC_DMAC,
200  DMA_TT_PERF_TO_MEM_FC_PERF,
201  DMA_TT_PERF_TO_PERF_FC_SRC_FC_PERF,
202  DMA_TT_MEM_TO_PERF_FC_PERF,
203  DMA_TT_PERF_TO_PERF_FC_DST_PERF,
204 };
205 
206 enum dma_ahb_master {
207  DMA_AHB_MASTER_MEM,
208  DMA_AHB_MASTER_PERIPH,
209 };
210 
211 enum dma_pcm_error_code {
212  DMA_PCM_ERR_OK,
213  DMA_PCM_ERR_BUSY,
214  DMA_PCM_ERR_INVALID_PARA,
215  DMA_PCM_ERR_DMA_BUSY,
216  DMA_PCM_ERR_DMA_TRAN,
217 
218 };
219 
220 /*
221  * Data Structure
222  ****************************************************************************************
223  */
225 typedef struct {
226  uint32_t sar;
227  uint32_t dar;
228  uint32_t llp;
229  union {
230  struct {
231  uint32_t int_en:1;
232  uint32_t dst_tr_width:3;
233  uint32_t src_tr_width:3;
234  uint32_t dinc:2;
235  uint32_t sinc:2;
236  uint32_t dest_mszie:3;
237  uint32_t src_mszie:3;
238  uint32_t src_gather_en:1;
239  uint32_t dst_scatter_en:1;
240  uint32_t reserve1:1;
241  uint32_t tt_fc:3;
242  uint32_t dms:2;
243  uint32_t sms:2;
244  uint32_t llp_dst_en:1;
245  uint32_t llp_src_en:1;
246  uint32_t reserve2:2;
247  } u;
248  uint32_t word;
249  } ctl_l;
250  uint32_t ctl_h;
251  uint32_t sstat;
252  uint32_t dstat;
253 } dma_bd_t;
254 
255 /*
256  * Inline Functions
257  ****************************************************************************************
258  */
259 static __inline void dma_enable(uint32_t base)
260 {
261  WR_WORD((base + DMA_REG_CFG_OFS), 1);
262 }
263 
264 static __inline void dma_disable(uint32_t base)
265 {
266  WR_WORD((base + DMA_REG_CFG_OFS), 0);
267 }
268 
269 static __inline uint32_t dma_get_ch_enable(uint32_t base)
270 {
271  return RD_WORD(base + DMA_REG_CH_EN_OFS);
272 }
273 
274 static __inline void dma_ch_enable(uint32_t base, int chn)
275 {
276  uint32_t reg;
277 
278  reg = (1<<chn) | (1<<(chn+8));
279 
280  WR_WORD((base + DMA_REG_CH_EN_OFS), reg);
281 }
282 
283 static __inline void dma_ch_disable(uint32_t base, uint32_t ch_base, int chn)
284 {
285  uint32_t reg = RD_WORD(base + DMA_REG_CH_EN_OFS);
286 
287  if ((reg >> chn) & 1) {
288  uint32_t cfg_reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
289  if (!(cfg_reg & DMA_CH_CFG_FIFO_EMPTY)) {
290  cfg_reg |= DMA_CH_CFG_SUSP;
291  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, cfg_reg);
292  while (!(RD_WORD(ch_base + DMA_CH_REG_CFG_OFS) & DMA_CH_CFG_FIFO_EMPTY));
293  }
294  reg = (1<<(chn+8));
295  WR_WORD((base + DMA_REG_CH_EN_OFS), reg);
296  }
297 }
298 
299 static __inline uint32_t dma_intr_raw_tfr_status(uint32_t base)
300 {
301  return RD_WORD(base + DMA_REG_INTR_RAW_TFR);
302 }
303 
304 static __inline uint32_t dma_intr_tfr_status(uint32_t base)
305 {
306  return RD_WORD(base + DMA_REG_INTR_STAT_TFR);
307 }
308 
309 static __inline void dma_intr_tfr_clear(uint32_t base)
310 {
311  WR_WORD((base + DMA_REG_INTR_CLR_TFR), 0xFF);
312 }
313 
314 static __inline int dma_intr_ch_raw_tfr_status(uint32_t base, int chn)
315 {
316  return ((RD_WORD(base + DMA_REG_INTR_RAW_TFR) >> chn) & 1);
317 }
318 
319 static __inline int dma_intr_ch_tfr_status(uint32_t base, int chn)
320 {
321  return ((RD_WORD(base + DMA_REG_INTR_STAT_TFR) >> chn) & 1);
322 }
323 
324 static __inline void dma_intr_ch_tfr_clear(uint32_t base, int chn)
325 {
326  WR_WORD((base + DMA_REG_INTR_CLR_TFR), (1 << chn));
327 }
328 
329 static __inline uint32_t dma_intr_raw_block_status(uint32_t base)
330 {
331  return RD_WORD(base + DMA_REG_INTR_RAW_BLOCK);
332 }
333 
334 static __inline uint32_t dma_intr_block_status(uint32_t base)
335 {
336  return RD_WORD(base + DMA_REG_INTR_STAT_BLOCK);
337 }
338 
339 static __inline void dma_intr_block_clear(uint32_t base)
340 {
341  WR_WORD((base + DMA_REG_INTR_CLR_BLOCK), 0xFF);
342 }
343 
344 static __inline int dma_intr_ch_raw_block_status(uint32_t base, int chn)
345 {
346  return ((RD_WORD(base + DMA_REG_INTR_RAW_BLOCK) >> chn) & 1);
347 }
348 
349 static __inline int dma_intr_ch_block_status(uint32_t base, int chn)
350 {
351  return ((RD_WORD(base + DMA_REG_INTR_STAT_BLOCK) >> chn) & 1);
352 }
353 
354 static __inline void dma_intr_ch_block_clear(uint32_t base, int chn)
355 {
356  WR_WORD((base + DMA_REG_INTR_CLR_BLOCK), (1 << chn));
357 }
358 
359 
360 static __inline uint32_t dma_intr_raw_src_status(uint32_t base)
361 {
362  return RD_WORD(base + DMA_REG_INTR_RAW_SRC);
363 }
364 
365 static __inline uint32_t dma_intr_src_status(uint32_t base)
366 {
367  return RD_WORD(base + DMA_REG_INTR_STAT_SRC);
368 }
369 
370 static __inline void dma_intr_src_clear(uint32_t base)
371 {
372  WR_WORD((base + DMA_REG_INTR_CLR_SRC), 0xFF);
373 }
374 
375 static __inline int dma_intr_ch_raw_src_status(uint32_t base, int chn)
376 {
377  return ((RD_WORD(base + DMA_REG_INTR_RAW_SRC) >> chn) & 1);
378 }
379 
380 static __inline int dma_intr_ch_src_status(uint32_t base, int chn)
381 {
382  return ((RD_WORD(base + DMA_REG_INTR_STAT_SRC) >> chn) & 1);
383 }
384 
385 static __inline void dma_intr_ch_src_clear(uint32_t base, int chn)
386 {
387  WR_WORD((base + DMA_REG_INTR_CLR_SRC), (1 << chn));
388 }
389 
390 static __inline uint32_t dma_intr_raw_dst_status(uint32_t base)
391 {
392  return RD_WORD(base + DMA_REG_INTR_RAW_DST);
393 }
394 
395 static __inline uint32_t dma_intr_dst_status(uint32_t base)
396 {
397  return RD_WORD(base + DMA_REG_INTR_STAT_DST);
398 }
399 
400 static __inline void dma_intr_dst_clear(uint32_t base)
401 {
402  WR_WORD((base + DMA_REG_INTR_CLR_DST), 0xFF);
403 }
404 
405 static __inline int dma_intr_ch_raw_dst_status(uint32_t base, int chn)
406 {
407  return ((RD_WORD(base + DMA_REG_INTR_RAW_DST) >> chn) & 1);
408 }
409 
410 static __inline int dma_intr_ch_dst_status(uint32_t base, int chn)
411 {
412  return ((RD_WORD(base + DMA_REG_INTR_STAT_DST) >> chn) & 1);
413 }
414 
415 static __inline void dma_intr_ch_dst_clear(uint32_t base, int chn)
416 {
417  WR_WORD((base + DMA_REG_INTR_CLR_DST), (1 << chn));
418 }
419 
420 static __inline uint32_t dma_intr_raw_err_status(uint32_t base)
421 {
422  return RD_WORD(base + DMA_REG_INTR_RAW_ERR);
423 }
424 
425 static __inline uint32_t dma_intr_err_status(uint32_t base)
426 {
427  return RD_WORD(base + DMA_REG_INTR_STAT_ERR);
428 }
429 
430 static __inline void dma_intr_err_clear(uint32_t base)
431 {
432  WR_WORD((base + DMA_REG_INTR_CLR_ERR), 0xFF);
433 }
434 
435 static __inline int dma_intr_ch_raw_err_status(uint32_t base, int chn)
436 {
437  return ((RD_WORD(base + DMA_REG_INTR_RAW_ERR) >> chn) & 1);
438 }
439 
440 static __inline int dma_intr_ch_err_status(uint32_t base, int chn)
441 {
442  return ((RD_WORD(base + DMA_REG_INTR_STAT_ERR) >> chn) & 1);
443 }
444 
445 static __inline void dma_intr_ch_err_clear(uint32_t base, int chn)
446 {
447  WR_WORD((base + DMA_REG_INTR_CLR_ERR), (1 << chn));
448 }
449 
450 static __inline void dma_intr_raw_clear_all(uint32_t base)
451 {
452  WR_WORD(base + DMA_REG_INTR_CLR_TFR, 0xFF);
453  WR_WORD(base + DMA_REG_INTR_CLR_BLOCK, 0xFF);
454  WR_WORD(base + DMA_REG_INTR_CLR_SRC, 0xFF);
455  WR_WORD(base + DMA_REG_INTR_CLR_DST, 0xFF);
456  WR_WORD(base + DMA_REG_INTR_CLR_ERR, 0xFF);
457 
458  return;
459 }
460 
461 static __inline void dma_intr_clr(uint32_t base, int chn, uint32_t status)
462 {
463  if (status & DMA_IT_STATUS_TFR) {
464  WR_WORD((base + DMA_REG_INTR_CLR_TFR), (1 << chn));
465  }
466 
467  if (status & DMA_IT_STATUS_BLOCK) {
468  WR_WORD((base + DMA_REG_INTR_CLR_BLOCK), (1 << chn));
469  }
470 
471  if (status & DMA_IT_STATUS_SRCT) {
472  WR_WORD((base + DMA_REG_INTR_CLR_SRC), (1 << chn));
473  }
474 
475  if (status & DMA_IT_STATUS_DSTT) {
476  WR_WORD((base + DMA_REG_INTR_CLR_DST), (1 << chn));
477  }
478 
479  if (status & DMA_IT_STATUS_ERR) {
480  WR_WORD((base + DMA_REG_INTR_CLR_ERR), (1 << chn));
481  }
482 }
483 
484 static __inline void dma_intr_mask(uint32_t base, int chn, uint32_t mask)
485 {
486 
487  if (mask & DMA_IT_STATUS_TFR) {
488  WR_WORD((base + DMA_REG_INTR_MASK_TFR), (1<<(chn+8)));
489  }
490 
491  if (mask & DMA_IT_STATUS_BLOCK) {
492  WR_WORD((base + DMA_REG_INTR_MASK_BLOCK), (1<<(chn+8)));
493  }
494 
495  if (mask & DMA_IT_STATUS_SRCT) {
496  WR_WORD((base + DMA_REG_INTR_MASK_SRC), (1<<(chn+8)));
497  }
498 
499  if (mask & DMA_IT_STATUS_DSTT) {
500  WR_WORD((base + DMA_REG_INTR_MASK_DST), (1<<(chn+8)));
501  }
502 
503  if (mask & DMA_IT_STATUS_ERR) {
504  WR_WORD((base + DMA_REG_INTR_MASK_ERR), (1<<(chn+8)));
505  }
506 }
507 
508 static __inline void dma_intr_unmask(uint32_t base, int chn, uint32_t mask)
509 {
510 
511  if (mask & DMA_IT_STATUS_TFR) {
512  WR_WORD((base + DMA_REG_INTR_MASK_TFR), ((1<<chn) | (1<<(chn+8))));
513  }
514 
515  if (mask & DMA_IT_STATUS_BLOCK) {
516  WR_WORD((base + DMA_REG_INTR_MASK_BLOCK), ((1<<chn) | (1<<(chn+8))));
517  }
518 
519  if (mask & DMA_IT_STATUS_SRCT) {
520  WR_WORD((base + DMA_REG_INTR_MASK_SRC), ((1<<chn) | (1<<(chn+8))));
521  }
522 
523  if (mask & DMA_IT_STATUS_DSTT) {
524  WR_WORD((base + DMA_REG_INTR_MASK_DST), ((1<<chn) | (1<<(chn+8))));
525  }
526 
527  if (mask & DMA_IT_STATUS_ERR) {
528  WR_WORD((base + DMA_REG_INTR_MASK_ERR), ((1<<chn) | (1<<(chn+8))));
529  }
530 }
531 
532 static __inline void dma_sw_src_req(uint32_t base, int chn)
533 {
534  WR_WORD((base + DMA_REG_SRC_SW_REQ), ((1<<chn)|(1<<(8+chn))));
535 }
536 
537 static __inline void dma_sw_dst_req(uint32_t base, int chn)
538 {
539  WR_WORD((base + DMA_REG_DST_SW_REQ), ((1<<chn)|(1<<(8+chn))));
540 }
541 
542 static __inline void dma_sw_src_sreq(uint32_t base, int chn)
543 {
544  WR_WORD((base + DMA_REG_SRC_SW_SGLREQ), ((1<<chn)|(1<<(8+chn))));
545 }
546 
547 static __inline void dma_sw_dst_sreq(uint32_t base, int chn)
548 {
549  WR_WORD((base + DMA_REG_DST_SW_SGLREQ), ((1<<chn)|(1<<(8+chn))));
550 }
551 
552 static __inline void dma_sw_src_lreq(uint32_t base, int chn)
553 {
554  WR_WORD((base + DMA_REG_LST_SRC_SW_REQ), ((1<<chn)|(1<<(8+chn))));
555 }
556 
557 static __inline void dma_sw_dst_lreq(uint32_t base, int chn)
558 {
559  WR_WORD((base + DMA_REG_LST_DST_SW_REQ), ((1<<chn)|(1<<(8+chn))));
560 }
561 
562 static __inline void dma_ch_set_sar(uint32_t ch_base, uint32_t addr)
563 {
564  WR_WORD(ch_base + DMA_CH_REG_SAR_OFS, addr);
565 }
566 
567 static __inline void dma_ch_set_dar(uint32_t ch_base, uint32_t addr)
568 {
569  WR_WORD(ch_base + DMA_CH_REG_DAR_OFS, addr);
570 }
571 
572 static __inline void dma_ch_intr_enable(uint32_t ch_base)
573 {
574  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
575  reg |= DMA_CH_CTL_INT_EN;
576 
577  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
578 }
579 
580 static __inline void dma_ch_intr_disable(uint32_t ch_base)
581 {
582  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
583  reg &= ~DMA_CH_CTL_INT_EN;
584  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
585 }
586 
587 static __inline void dma_ch_dst_width(uint32_t ch_base, int data_width)
588 {
589  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
590  reg &= ~DMA_CH_CTL_DST_TR_WIDTH;
591  reg |= (data_width & 0x7) << 1;
592  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
593 }
594 
595 static __inline void dma_ch_src_width(uint32_t ch_base, int data_width)
596 {
597  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
598  reg &= ~DMA_CH_CTL_SRC_TR_WIDTH;
599  reg |= (data_width & 0x7) << 4;
600  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
601 }
602 
603 static __inline void dma_ch_dst_inc(uint32_t ch_base, int dinc)
604 {
605  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
606  reg &= ~DMA_CH_CTL_DINC;
607  reg |= (dinc & 0x3) << 7;
608  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
609 }
610 
611 static __inline void dma_ch_src_inc(uint32_t ch_base, int sinc)
612 {
613  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
614  reg &= ~DMA_CH_CTL_SINC;
615  reg |= (sinc & 0x3) << 9;
616  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
617 }
618 
619 static __inline void dma_ch_dst_msize(uint32_t ch_base, int msize)
620 {
621  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
622  reg &= ~DMA_CH_CTL_DEST_MSIZE;
623  reg |= (msize & 0x7) << 11;
624  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
625 }
626 
627 static __inline void dma_ch_src_msize(uint32_t ch_base, int msize)
628 {
629  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
630  reg &= ~DMA_CH_CTL_SRC_MSIZE;
631  reg |= (msize & 0x7) << 14;
632  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
633 }
634 
635 static __inline void dma_ch_tran_type_fc(uint32_t ch_base, int tt_fc)
636 {
637  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
638  reg &= ~DMA_CH_CTL_TT_FC;
639  reg |= (tt_fc & 0x7) << 20;
640  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
641 }
642 
643 static __inline void dma_ch_dst_ahb_master(uint32_t ch_base, int dms)
644 {
645  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
646  reg &= ~DMA_CH_CTL_DMS;
647  reg |= (dms & 0x3) << 23;
648  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
649 }
650 
651 static __inline void dma_ch_src_ahb_master(uint32_t ch_base, int sms)
652 {
653  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
654  reg &= ~DMA_CH_CTL_SMS;
655  reg |= (sms & 0x3) << 25;
656  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
657 }
658 
659 static __inline void dma_ch_llp_dst_en(uint32_t ch_base, int en)
660 {
661  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
662  if (en)
663  reg |= DMA_CH_CTL_LLP_DST_EN;
664  else
665  reg &= ~DMA_CH_CTL_LLP_DST_EN;
666 
667  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
668 }
669 
670 static __inline void dma_ch_llp_src_en(uint32_t ch_base, int en)
671 {
672  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS);
673  if (en)
674  reg |= DMA_CH_CTL_LLP_SRC_EN;
675  else
676  reg &= ~DMA_CH_CTL_LLP_SRC_EN;
677 
678  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS, reg);
679 }
680 
681 static __inline void dma_ch_tran_block_size(uint32_t ch_base, int block_ts)
682 {
683  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS + 4);
684  reg &= ~DMA_CH_CTL_BLOCK_TS;
685  reg |= block_ts;
686  WR_WORD(ch_base + DMA_CH_REG_CTL_OFS + 4, reg);
687 }
688 
689 static __inline uint32_t dma_ch_get_tran_block_size(uint32_t ch_base)
690 {
691  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CTL_OFS + 4);
692  reg &= DMA_CH_CTL_BLOCK_TS;
693  return reg;
694 }
695 
696 static __inline void dma_ch_set_prio(uint32_t ch_base, int priority)
697 {
698  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
699  reg &= ~DMA_CH_CFG_PRIOR;
700  reg |= (priority & 0x7) << 5;
701  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
702 }
703 
704 static __inline int dma_ch_get_prio(uint32_t ch_base)
705 {
706  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
707  reg >>= 5;
708  reg &= 0x7;
709 
710  return (int)reg;
711 }
712 
713 static __inline int dma_ch_fifo_empty(uint32_t ch_base)
714 {
715  return (((RD_WORD(ch_base + DMA_CH_REG_CFG_OFS) & DMA_CH_CFG_FIFO_EMPTY) ? 1 : 0));
716 }
717 
718 static __inline void dma_ch_suspend(uint32_t ch_base)
719 {
720  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
721 
722  reg |= DMA_CH_CFG_SUSP;
723 
724  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
725 
726  while (!dma_ch_fifo_empty(ch_base));
727 }
728 
729 static __inline void dma_ch_hs_dest(uint32_t ch_base, int hw)
730 {
731  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
732 
733  if (hw) {
734  reg &= ~DMA_CH_CFG_HS_SEL_DST;
735  } else {
736  reg |= DMA_CH_CFG_HS_SEL_DST;
737  }
738 
739  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
740 }
741 
742 static __inline void dma_ch_hs_src(uint32_t ch_base, int hw)
743 {
744  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
745 
746  if (hw) {
747  reg &= ~DMA_CH_CFG_HS_SEL_SRC;
748  } else {
749  reg |= DMA_CH_CFG_HS_SEL_SRC;
750  }
751 
752  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
753 }
754 
755 static __inline void dma_ch_hs_pol_dest(uint32_t ch_base, int active_high)
756 {
757  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
758 
759  if (active_high) {
760  reg &= ~DMA_CH_CFG_DST_HS_POL;
761  } else {
762  reg |= DMA_CH_CFG_DST_HS_POL;
763  }
764 
765  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
766 }
767 
768 static __inline void dma_ch_hs_pol_src(uint32_t ch_base, int active_high)
769 {
770  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
771 
772  if (active_high) {
773  reg &= ~DMA_CH_CFG_SRC_HS_POL;
774  } else {
775  reg |= DMA_CH_CFG_SRC_HS_POL;
776  }
777 
778  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
779 }
780 
781 static __inline void dma_ch_sar_reload(uint32_t ch_base, int reload)
782 {
783  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
784 
785  if (reload) {
786  reg |= DMA_CH_CFG_RELOAD_SRC;
787  } else {
788  reg &= ~DMA_CH_CFG_RELOAD_SRC;
789  }
790 
791  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
792 }
793 
794 static __inline void dma_ch_dest_reload(uint32_t ch_base, int reload)
795 {
796  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS);
797 
798  if (reload) {
799  reg |= DMA_CH_CFG_RELOAD_DST;
800  } else {
801  reg &= ~DMA_CH_CFG_RELOAD_DST;
802  }
803 
804  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS, reg);
805 }
806 
807 static __inline void dma_ch_fc(uint32_t ch_base, int pre_fetch)
808 {
809  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4);
810 
811  if (pre_fetch) {
812  reg &= ~DMA_CH_CFG_FCMODE;
813  } else {
814  reg |= DMA_CH_CFG_FCMODE;
815  }
816 
817  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4, reg);
818 }
819 
820 static __inline void dma_ch_fifo(uint32_t ch_base, int single)
821 {
822  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4);
823 
824  if (single) {
825  reg &= ~DMA_CH_CFG_FIFO_MODE;
826  } else {
827  reg |=~DMA_CH_CFG_FIFO_MODE;
828  }
829 
830  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4, reg);
831 }
832 
833 static __inline void dma_ch_src_periph_id(uint32_t ch_base, int id)
834 {
835  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4);
836 
837  reg &= ~DMA_CH_CFG_SRC_PER;
838  reg |= (id << 7);
839  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4, reg);
840 }
841 
842 static __inline void dma_ch_dest_periph_id(uint32_t ch_base, int id)
843 {
844  uint32_t reg = RD_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4);
845 
846  reg &= ~DMA_CH_CFG_DEST_PER;
847  reg |= (id << 11);
848  WR_WORD(ch_base + DMA_CH_REG_CFG_OFS + 4, reg);
849 }
850 
851 static __inline void dma_ch_llp(uint32_t ch_base, uint32_t addr)
852 {
853  WR_WORD(ch_base + DMA_CH_REG_LLP_OFS, addr);
854 }
855 
856 static __inline uint32_t dma_ch_get_llp(uint32_t ch_base)
857 {
858  return (RD_WORD(ch_base + DMA_CH_REG_LLP_OFS) & 0xFFFFFFFC);
859 }
860 
861 
862 /*
863  * Inline Functions
864  ****************************************************************************************
865  */
866 
890 void *hal_dma_open(int id, int periph_id, uint32_t sar, uint32_t dar, int size, int sdw, int ddw, int sai, int dai, int sbz, int dbz, int sahb, int dahb, int ttype);
891 
913 void *hal_dma_soft_open(int id, uint32_t sar, uint32_t dar, int size, int sdw, int ddw, int sai, int dai, int sbz, int dbz, int sahb, int dahb, int ttype);
914 
925 void hal_dma_close(void *hdl);
926 
939 int hal_dma_ch_enable(void *hdl, void *arg, void (*callback)(int id, void *arg, uint32_t status));
940 int hal_dma_soft_ch_enable(void *hdl, void *arg, void (*callback)(int id, void *arg, uint32_t status));
941 
952 int hal_dma_ch_disable(void *hdl);
953 
960 char hal_dma_ch_is_enabled(void *hdl);
961 
975 int hal_dma_switch_buffer(void *hdl, int sa_da, uint32_t buffer_addr);
976 
986 int hal_dma_src_req(void *hdl);
987 int hal_dma_dst_req(void *hdl);
988 
998 uint32_t hal_dma_get_tran_len(void *hdl);
999 
1000 
1024 int hal_dma_add_mb_item(uint32_t ba, uint32_t next_ba, uint32_t dar, uint32_t sar, int dtw, int stw, int dai, int sai, int dbz, int sbz, int dms, int sms, int tt_fc, int size);
1025 
1039 void *hal_dma_mb_open(int id, uint32_t bd_addr, int bda_nb, int src_periph_id, int dst_periph_id);
1040 
1041 
1053 int hal_dma_mb_ch_enable(void *hdl, void *arg, void (*callback)(int id, void *arg, uint32_t status));
1054 int hal_dma_mb_ch_enable_no_int(void *hdl);
1055 
1056 
1067 int hal_dma_mb_ch_disable(void *hdl, uint32_t baddr);
1068 int hal_dma_mb_ch_disable_no_int(void *hdl);
1069 
1070 
1086 int hal_dma_pcm_en(void *buffer0, void *buffer1, uint16_t buffer_len, void *arg, void (*callback)(void * arg, int id, uint32_t status));
1087 int hal_dma_pcm_dis(void);
1088 
1089 int hal_dma_set_sar(void *hdl, uint32_t sar);
1090 int hal_dma_set_dar(void *hdl, uint32_t dar);
1091 int hal_dma_set_tran_block_size(void *hdl, uint32_t size);
1092 
1093 int hal_dma_ch_enable_no_int(void *hdl);
1094 int hal_dma_ch_disable_no_int(void *hdl);
1095 int hal_dma_poll_tran_done(void *hdl, int max_poll_nb);
1096 
1097 
1098 
1100 
1101 #endif // HAL_DMA_H
hal_dma_switch_buffer
int hal_dma_switch_buffer(void *hdl, int sa_da, uint32_t buffer_addr)
DMA change source or destination buffer address : This function is provided to quickly switch buffer ...
hal_dma_mb_ch_disable
int hal_dma_mb_ch_disable(void *hdl, uint32_t baddr)
DMA link list driver open.
hal_dma_ch_disable
int hal_dma_ch_disable(void *hdl)
DMA channel disable.
hal_dma_mb_open
void * hal_dma_mb_open(int id, uint32_t bd_addr, int bda_nb, int src_periph_id, int dst_periph_id)
DMA block chaining open.
hal_dma_get_tran_len
uint32_t hal_dma_get_tran_len(void *hdl)
Get DMA transfer length.
dma_bd_t
DMA block descriptor structure.
Definition: hal_dma.h:225
hal_dma_open
void * hal_dma_open(int id, int periph_id, uint32_t sar, uint32_t dar, int size, int sdw, int ddw, int sai, int dai, int sbz, int dbz, int sahb, int dahb, int ttype)
Open the DMA driver.
hal_dma_add_mb_item
int hal_dma_add_mb_item(uint32_t ba, uint32_t next_ba, uint32_t dar, uint32_t sar, int dtw, int stw, int dai, int sai, int dbz, int sbz, int dms, int sms, int tt_fc, int size)
Add DMA each block descriptor for block chaining : Call this function before start DMA block chaining...
hal_dma_soft_open
void * hal_dma_soft_open(int id, uint32_t sar, uint32_t dar, int size, int sdw, int ddw, int sai, int dai, int sbz, int dbz, int sahb, int dahb, int ttype)
Open a Software Control DMA driver.
hal_dma_mb_ch_enable
int hal_dma_mb_ch_enable(void *hdl, void *arg, void(*callback)(int id, void *arg, uint32_t status))
DMA link list driver open.
hal_dma_ch_enable
int hal_dma_ch_enable(void *hdl, void *arg, void(*callback)(int id, void *arg, uint32_t status))
(Software Control) DMA channel enable
hal_dma_ch_is_enabled
char hal_dma_ch_is_enabled(void *hdl)
DMA channel is enabled.
hal_dma_close
void hal_dma_close(void *hdl)
Close the DMA driver.
hal_dma_pcm_en
int hal_dma_pcm_en(void *buffer0, void *buffer1, uint16_t buffer_len, void *arg, void(*callback)(void *arg, int id, uint32_t status))
DMA Audio block&#39;s PCM data to memory : This function is not responsible for setting up Audio Block&#39;s ...
hal_dma_src_req
int hal_dma_src_req(void *hdl)
DMA controlled by software to transfer data from or to peripheral.