hal_crc.h

#ifndef HAL_CRC_H
#define HAL_CRC_H
#include "in_mmap.h"
#include <stdint.h>
#if !CFG_NO_OS
#include "cmsis_os.h"
#endif
#include "./hal/hal_power.h"
#define CRC_OUT_MASK8       (0xFFU)
#define CRC_OUT_MASK16      (0xFFFFU)
#define CRC_OUT_MASK24      (0xFFFFFFU)
#define CRC_OUT_MASK32      (0xFFFFFFFFU)
enum crc_error {
    CRC_ERR_OK = 0,
    CRC_ERR_INVALID_PARAM = -1,
    CRC_ERR_TIMEOUT = -2,
    CRC_ERR_BUSY = -3,
    CRC_ERR_UNSPEC = -4,
};

typedef enum {
    CRC_32 = 0,
    CRC_16CCITT,
    CRC_CUSTOM,
} crc_mode_t;

typedef enum crc_input_bytes {
    CRC_1_BYTE = 0,
    CRC_2_BYTE = 1,
    CRC_3_BYTE = 2,
    CRC_4_BYTE = 3
} crc_input_bytes_t;

enum crc_poly {
    CRC_POLY_8 = 0,
    CRC_POLY_16,
    CRC_POLY_24,
    CRC_POLY_32,
};
enum crc_order {
    CRC_MSB = 0,
    CRC_LSB,
};


typedef struct {
    int mode;
    int irq_prio;
    int en_dma;
    void *arg;
    void (*callback)(void* arg);
    
} crc_init_t;
typedef struct crc_conf {
    char bit_order;
    char byte_order;
    uint8_t bit_rev;
    uint8_t byte_rev;
    uint8_t append_zero;
    char poly_order;
    char output_len;
    char pad;
    uint32_t poly_val;
    uint32_t init_val;
    uint32_t init_xor_val;
    uint32_t final_xor_val;
    
} crc_conf_t;

typedef struct {
    void *arg;
    void (*callback)(void* arg);
    char irq_prio;
    char en_dma;
    char used;
    char start;
    char en_isr;
    char output_len;
    char pad[2];
    crc_conf_t cfg;
#if !CFG_NO_OS
    osSemaphoreId semaphore;
    osMutexId mutex;
#endif  // !CFG_NO_OS
#if CFG_PM_EN
    int resume;
    int power_state;
    struct pm_module pmd;
#endif  
} crc_dev_t;

static __inline void crc_clk_enble(int en)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (en) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_CLK_ENABLE;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_CLK_ENABLE;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_enble(int en)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (en) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_ENABLE;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_ENABLE;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_start(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_START;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_START;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_stop(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_STOP;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_STOP;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_shiftin_bit_order(int lsb)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (lsb) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_SHIFTIN_BIT_ORDER;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_SHIFTIN_BIT_ORDER;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_shiftin_byte_order(int lsb)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (lsb) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_SHIFTIN_BYTE_ORDER;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_SHIFTIN_BYTE_ORDER;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_final_bit_rev(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_BIT_REVERSE;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_BIT_REVERSE;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_final_byte_rev(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_BYTE_REVERSE;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_BYTE_REVERSE;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_append_zero(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_APPEND_ZERO;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_FINAL_APPEND_ZERO;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_dma_enble(int en)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (en) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_DMA_ENABLE;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_DMA_ENABLE;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_unknow_input_len(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_UNKNOWN_INPUT_LENGTH;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_UNKNOWN_INPUT_LENGTH;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_clr_total_byte_cnt(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    if (val) {
        reg |= PWM_REGS_CRC_MISC_CTRL_CTL_CRC_CLR_TOTAL_BYTE_CNT;
    } else {
        reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_CLR_TOTAL_BYTE_CNT;
    }
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_poly_order(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_MISC_CTRL);
    reg &= ~PWM_REGS_CRC_MISC_CTRL_CTL_CRC_POLY_ORDER;
    reg |= (val&PWM_REGS_CRC_MISC_CTRL_CTL_CRC_POLY_ORDER_MASK)<<PWM_REGS_CRC_MISC_CTRL_CTL_CRC_POLY_ORDER_SHIFT;
    WR_WORD(PWM_REGS_CRC_MISC_CTRL, reg);
}
static __inline void crc_poly(uint32_t val)
{
    WR_WORD(PWM_REGS_CRC_POLY, val);
}
static __inline void crc_init_val(uint32_t val)
{
    WR_WORD(PWM_REGS_CRC_INIT_VAL, val);
}
static __inline void crc_init_xor_val(uint32_t val)
{
    WR_WORD(PWM_REGS_CRC_INIT_XOR_VAL, val);
}
static __inline void crc_final_xor_val(uint32_t val)
{
    WR_WORD(PWM_REGS_CRC_FINAL_XOR_VAL, val);
}
static __inline void crc_input_num_byte(int num)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_INPUT_INFO);
    reg &= ~PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_NUM_BYTE;
    reg |= (num&PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_NUM_BYTE_MASK)<<PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_NUM_BYTE_SHIFT;
    WR_WORD(PWM_REGS_CRC_INPUT_INFO, reg);
}
static __inline void crc_input_last(int val)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_INPUT_INFO);
    if (val)
        reg |= PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_LAST;
    else
        reg &= ~PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_LAST;
    WR_WORD(PWM_REGS_CRC_INPUT_INFO, reg);  
}
static __inline uint32_t crc_wait_input(void)
{
    return (RD_WORD(PWM_REGS_CRC_INPUT_INFO)>>3)&0x1;

}
static __inline void crc_input_total_byte(uint32_t num)
{
    uint32_t reg = RD_WORD(PWM_REGS_CRC_INPUT_INFO);
    reg &= ~PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_TOTAL_NUM_BYTE;
    reg |= (num&PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_TOTAL_NUM_BYTE_MASK)<<PWM_REGS_CRC_INPUT_INFO_CTL_CRC_INPUT_TOTAL_NUM_BYTE_SHIFT;
    WR_WORD(PWM_REGS_CRC_INPUT_INFO, reg);  
}
static __inline void crc_input(uint32_t val)
{
    WR_WORD(PWM_REGS_CRC_INPUT, val);
}
static __inline uint32_t crc_curr_status(void)
{
    return RD_WORD(PWM_REGS_CRC_STATUS)&PWM_REGS_CRC_STATUS_STS_CRC_CURR_STATUS_MASK;
}
static __inline uint32_t crc_curr_done(void)
{
    return (RD_WORD(PWM_REGS_CRC_STATUS)&PWM_REGS_CRC_STATUS_STS_CRC_DONE)>>8;
}
static __inline uint32_t crc_curr_byte_cnt(void)
{
    return RD_WORD(PWM_REGS_CRC_STATUS)&PWM_REGS_CRC_BYTE_CNT_STS_CRC_CURR_BYTE_CNT_SHIFT;
}
static __inline uint32_t crc_value(void)
{
    return RD_WORD(PWM_REGS_CRC_VALUE);
}
int hal_crc_open(crc_init_t *init);

int hal_crc_close(void);

int hal_crc_start(uint8_t *buf, uint32_t len, uint32_t *crc_val);

int hal_crc_stream_start(void);

int hal_crc_stream_input(uint8_t *buf, uint32_t len, int last);

int hal_crc_stream_end(uint32_t *crc_val);

int hal_crc_cfg(crc_conf_t *conf);
int hal_crc_open_status(void);
int hal_crc_isr_status(void);

#endif