hal_counter.h

#ifndef HAL_COUNTER_H
#define HAL_COUNTER_H

#include "./hal/hal_power.h"

#include "in_mmap.h"
#include <stdint.h>
//#define APB_CLOCK 32000000

#define CNT0_BASE (0)
#define CNT1_BASE (0x100)
#define CNT2_BASE (0x200)
#define CNT3_BASE (0x300)

#define CNT_CAPTURE_SHIFTIN_MODE 0x0
#define CNT_WAVEFORM_SHITOUT_MODE 0x1
#define CNT_COUNT_MODE 0x0
#define CNT_SHIFT_MODE 0x2
#define CNT_SWITCH_DISABLE 0x0
#define CNT_SWITCH_ENABLE 0x4

#define CNT_CAPTURE_MODE (CNT_CAPTURE_SHIFTIN_MODE | CNT_COUNT_MODE)
#define CNT_WAVAFORM_MODE (CNT_WAVEFORM_SHITOUT_MODE | CNT_COUNT_MODE)
#define CNT_SHIFTIN_MODE (CNT_CAPTURE_SHIFTIN_MODE | CNT_SHIFT_MODE)
#define CNT_SHIFTOUT_MODE (CNT_WAVEFORM_SHITOUT_MODE | CNT_SHIFT_MODE)

//enable_c0
#define CNT_ENABLE 0x1UL
#define CNT_CLK_INV_ENABLE 0x1000UL
#define CNT_CLK_ENABLE 0x2000UL
#define CNT_CLK_DIV8 0  
#define CNT_CLK_DIV4 1  
#define CNT_CLK_DIV2 2  
#define CNT_CLK_32K 3
#define CNT_EXT_CLK0 4
#define CNT_EXT_CLK1 5
#define CNT_EXT_CLK2 6

/* For count0, clk0 is count1, clk1 is count2, clk2 is count3.
    For count1, clk0 is count0, clk1 is count2, clk2 is count3 */
#define CNT_COUNTER_CLK0 7
#define CNT_COUNTER_CLK1 8
#define CNT_COUNTER_CLK2 9

//src_sel_start_c0
#define CNT_EXT_DIN_A 1
#define CNT_EXT_DIN_B 2
#define CNT_GLOBAL_START_TRIGGER 3
#define CNT_SINGLE_START_TRIGGER 4
#define CNT_GLOBAL_STOP_TRIGGER 5
#define CNT_SINGLE_STOP_TRIGGER 6
#define CNT_INNER_DIN0 11
#define CNT_INNER_DIN1 12
#define CNT_INNER_DIN2 13
#define CNT_INNER_DIN3 14
#define CNT_START_SIGNLE_SHIFT 0
#define CNT_STOP_SIGNLE_SHIFT 8
#define CNT_DIN0_SHIFT 16
#define CNT_DIN1_SHIFT 24
#define CNT_RISING_EDGE 0
#define CNT_FALLING_EDGE 0x10UL
#define CNT_BOTH_EDGE 0x20UL

//ctrl_snap_c0  reverse
#define CNT_SNAP_SHADOW_MASK 0x1UL
#define CNT_SNAP_CAPTURE_A_MASK 0x2UL
#define CNT_SNAP_CAPTURE_B_MASK 0x4UL
#define CNT_SNAP_SHIFTIN_DATA_MASK 0x8UL
#define CNT_SNAP_CLEAR_MASK 0x10000UL

//TARGET_REG_CTRL
#define CNT_A2_KEEP_VALUE 0x1UL
#define CNT_A2_RESET_VALUE 0x0UL
#define CNT_A2_STOP_COUNTER 0x2UL
#define CNT_A2_RESTART_COUNTER 0x0UL
#define CNT_B2_KEEP_VALUE 0x4UL
#define CNT_B2_RESET_VALUE 0x0UL
#define CNT_B2_STOP_COUNTER 0x8UL
#define CNT_B2_RESTART_COUNTER 0x0UL
#define CNT_DOUT_A_RESET_VALUE_SHIFT 4
#define CNT_DOUT_B_RESET_VALUE_SHIFT 5

//ir_dout_bypass_c0
#define CNT_OUT_BYPASS_A 0x10000UL //Bypass pin A operation(AND, OR and NOT)
#define CNT_OUT_BYPASS_B 0x20000UL //Bypass pin B operation(AND, OR and NOT)
#define CNT_OPT_A_AND   0x0
#define CNT_OPT_A_OR    0x1
#define CNT_OPT_A_XOR   0x2
#define CNT_OPT_B_AND   0x0
#define CNT_OPT_B_OR    0x10
#define CNT_OPT_B_XOR   0x20

//ir_din_bypass_c0
#define CNT_IN_BYPASS_A 0x1UL
#define CNT_IN_BYPASS_B 0x2UL

//shiftmode_point_en_c0
#define CNT_SHIFTMODE_POINT_EN 0x10000

//waveform_mode_automatic_c0
#define CNT_WAVEFORM_SHIFTOUT_CNT_SHIFT 0
#define CNT_CAPTURE_SHIFTIN_CNT_SHIFT 8
#define CNT_WAVEFORM_SHIFTOUT_AUTO_ENABLE 0x10000UL
#define CNT_CAPTURE_SHIFTIN_AUTO_ENABLE 0x1000000UL

//interrupt
#define CNT0_SHIFT 0
#define CNT1_SHIFT 8
#define CNT2_SHIFT 16
#define CNT3_SHIFT 24
#define CNT_A_UPDATE 1
#define CNT_B_UPDATE 0x2
#define CNT_OVERFLOW 0x4
#define CNT_SHIFTIN_COMPLETE 0x8
#define CNT_SHIFTOUT_COMPLETE 0x10
#define CNT_WAVEFORM_STOP 0x20 //counter value reach a2 or b2
#define CNT_SHIFTIN_CAPTURE_END 0x40 //need enable auto switch
#define CNT_SHIFTOUT_WAVEFORM_END 0x80 //need enable auto swtich

//reset_ctrl_4
#define CNT_RESET_CNT0 0x00000010UL
#define CNT_RESET_CNT1 0x00000020UL
#define CNT_RESET_CNT2 0x00000040UL
#define CNT_RESET_CNT3 0x00000080UL

//mux sel
#define CNT0_BUS_B 0x1
#define CNT1_BUS_B 0x2
#define CNT2_BUS_B 0x4
#define CNT3_BUS_B 0x8


/* flip bit with mask */
#define FLIP_BIT(val, mask)            \
    do {                               \
        uint32_t _tmp = (~val) & mask; \
        val &= ~mask;                  \
        val |= _tmp;                   \
    } while (0)
#define DUMP_REG(reg, base) PRINTD(DBG_TRACE, #reg " %08x (%x)\n", RD_WORD(reg + base), base)
enum cnt_id {
    CNT0_ID = 0,
    CNT1_ID,
    CNT2_ID,
    CNT3_ID,
    CNT_MAX_ID,
};


enum cnt_int_pin {
    CNT0_PIN_A = 0,
    CNT0_PIN_B,
    CNT1_PIN_A,
    CNT1_PIN_B,
    CNT2_PIN_A,
    CNT2_PIN_B,
    CNT3_PIN_A,
    CNT3_PIN_B,
    CNT_MAX_PIN,
};

enum cnt_error {
    CNT_ERR_OK = 0,
    CNT_ERR_INVALID_PARAM = -1,
    CNT_ERR_TIMEOUT = -2,
};
typedef struct {
     int clk_div; /*<When use XO, clk can be 16000000, 8000000, 4000000. When use RC, clk can be 8000000, 4000000, 2000000.
                   CNT_CLK_DIV8 0  ///Root clock divide 8
                   CNT_CLK_DIV4 1  ///Root clock divide 4
                   CNT_CLK_DIV2 2  ///Root clock divide 2*/
     int prio;
     void *arg;
     void (*cb)(void *arg, uint32_t status);
} cnt_init_t;
typedef struct {
    uint32_t base;
    void (*cb)(void *arg, uint32_t status);
    void* arg;
    uint32_t clk;
    char id;
    char clk_div;
    char used;
    char prio; 
#if CFG_PM_EN
    int resume;
    int power_state;
    struct pm_module pmd;
#endif

} cnt_dev_t;

typedef void (*CNT_ISR_FUN)(void*, uint32_t);

static INLINE void cnt_enable_clk(uint32_t base)
{
    uint32_t reg = RD_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base);
    reg |= CNT_CLK_ENABLE;
    WR_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base, reg);
}
static INLINE void cnt_disable_clk(uint32_t base)
{
    uint32_t reg = RD_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base);
    reg &= ~CNT_CLK_ENABLE;
    WR_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base, reg);
}
static INLINE void cnt_set_clk(uint32_t base, uint32_t val)
{
    uint32_t reg = RD_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base);
    reg |= val << 8;
    WR_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base, reg);
}

static INLINE void cnt_set_mode(uint32_t base, uint32_t mode)
{
    WR_WORD(COUNTER_ALL_APB_REG_MODE_SEL_C0 + base, mode);
}
static INLINE void cnt_set_src_edge(uint32_t base, uint32_t src_edge)
{
    WR_WORD(COUNTER_ALL_APB_REG_SRC_SEL_EDGE_C0 + base, src_edge);
}
static INLINE void cnt_set_target_ctrl(uint32_t base, uint32_t ctrl)
{
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_CTRL_C0 + base, ctrl);
}
static INLINE void cnt_set_soft_trigger(uint32_t base, uint32_t trigger)
{
    WR_WORD(COUNTER_ALL_APB_REG_SOFT_TRIGGER_CTRL_C0 + base, trigger);
}
static INLINE void cnt_set_target_a(uint32_t base, uint32_t a0, uint32_t a1, uint32_t a2)
{
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_A0_C0 + base, a0);
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_A1_C0 + base, a1);
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_A2_C0 + base, a2);
}
static INLINE void cnt_set_target_b(uint32_t base, uint32_t b0, uint32_t b1, uint32_t b2)
{
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_B0_C0 + base, b0);
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_B1_C0 + base, b1);
    WR_WORD(COUNTER_ALL_APB_REG_TARGET_REG_B2_C0 + base, b2);
}
static INLINE void cnt_set_out_bypass(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_IR_DOUT_BYPASS_C0 + base, val);
}
static INLINE void cnt_set_in_bypass(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_IR_DIN_BYPASS_C0 + base, val);
}
static INLINE void cnt_set_input_mux(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_MUX_SEL_C0 + base, val);
}
static INLINE void cnt_set_shiftmode_ctrl(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTMODE_CTRL_C0 + base, val);
}

/* shiftin n bits*/
static INLINE void cnt_set_shiftin_bit_num(uint32_t base, uint32_t n)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTIN_DATA_CTRL_BITCNTS_C0 + base, n);
}

/* enable and sample point*/
static INLINE void cnt_set_shiftmode_point_en(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTMODE_POINT_EN_C0 + base, val);
}

static INLINE void cnt_set_one_bit_count(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_SWITCH_MODE_ONEBIT_CNTS_C0 + base, val);
}

static INLINE void cnt_set_one_cycle_value(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_IR_DIN_ONECYCLE_VALUE_A_C0 + base, val);
}
static INLINE void cnt_config_switch_mode(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_WAVEFORM_MODE_AUTOMATIC_C0 + base, val);
}

static INLINE uint32_t cnt_get_shiftin_update(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_SHIFTIN_DATABITS_UPDATED_C0 + base);
}

static INLINE uint32_t cnt_get_shiftin_data(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_SHIFTIN_DATA_C0 + base);
}
/* shiftout n bits, start from zero*/
static INLINE void cnt_set_shiftout_bit_num(uint32_t base, uint32_t n)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTOUT_DATA_CTRL_BITCNTS_C0 + base, n);
}
static INLINE void cnt_set_shiftout_data(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTOUT_DATA_C0 + base, val);
}
static INLINE void cnt_set_shiftout_data_valid(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_SHIFTOUT_DATA_VALID_C0 + base, val);
}

static INLINE uint32_t cnt_get_shadow_reg(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_SHADOW_REG_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_a0(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_A0_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_a1(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_A1_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_a2(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_A2_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_b0(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_B0_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_b1(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_B1_C0 + base);
}
static INLINE uint32_t cnt_get_capture_reg_b2(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_B2_C0 + base);
}
static INLINE uint32_t cnt_get_capture_status(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_STATUS_C0 + base);
}
static INLINE void cnt_set_capture_overflow(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_CAPTURE_REG_OVERFLOW_CTRL_C0 + base, val);
}
static INLINE uint32_t cnt_get_din_mux()
{
    return RD_WORD(COUNTER_ALL_APB_REG_DIN_MUX_SEL);
}
static INLINE uint32_t cnt_get_dout_mux()
{
    return RD_WORD(COUNTER_ALL_APB_REG_DOUT_MUX_SEL);
}
static INLINE void cnt_set_din_mux(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_DIN_MUX_SEL, val);
}
static INLINE void cnt_set_dout_mux(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_DOUT_MUX_SEL, val);
}
static INLINE void cnt_set_dout_enable_ctrl(uint32_t base, uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_DOUT_ENABLE_CTRL + base, val);
}
static INLINE uint32_t cnt_get_dout_enable_ctrl(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_DOUT_ENABLE_CTRL + base);
}
static INLINE void cnt_enable(uint32_t base)
{
    uint32_t reg = RD_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base);

    reg |= CNT_ENABLE;
    WR_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base, reg);
}
static INLINE void cnt_disable(uint32_t base)
{
    uint32_t reg = RD_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base);
    reg &= ~CNT_ENABLE;
    WR_WORD(COUNTER_ALL_APB_REG_ENABLE_C0 + base, reg);
}
static INLINE void cnt_trigger_start(uint32_t base)
{
    //unsigned int reg = RD_WORD(COUNTER_ALL_APB_REG_SINGLE_START_TRIGGER_C0 + base);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_START_TRIGGER_C0 + base, 1);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_START_TRIGGER_C0 + base, 0);
}
static INLINE void cnt_trigger_stop(uint32_t base)
{
    //unsigned int reg = RD_WORD(COUNTER_ALL_APB_REG_SINGLE_STOP_TRIGGER_C0 + base);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_STOP_TRIGGER_C0 + base, 1);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_STOP_TRIGGER_C0 + base, 0);
}
static INLINE void cnt_trigger_clear(uint32_t base) // clear to 0x0
{
    //unsigned int reg = RD_WORD(COUNTER_ALL_APB_REG_SINGLE_START_TRIGGER_C0 + base);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_CLEAR_TRIGGER_C0 + base, 1);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_CLEAR_TRIGGER_C0 + base, 0);
}
static INLINE void cnt_trigger_reset(uint32_t base) // equal to stop + clear
{
    //unsigned int reg = RD_WORD(COUNTER_ALL_APB_REG_SINGLE_STOP_TRIGGER_C0 + base);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_RESET_TRIGGER_C0 + base, 1);
    WR_WORD(COUNTER_ALL_APB_REG_SINGLE_RESET_TRIGGER_C0 + base, 0);
}
static INLINE void cnt_set_snap_ctrl(uint32_t base, uint32_t mask)
{
    uint32_t snap = RD_WORD(COUNTER_ALL_APB_REG_CTRL_SNAP_C0 + base);
    FLIP_BIT(snap, mask);
    WR_WORD(COUNTER_ALL_APB_REG_CTRL_SNAP_C0 + base, snap);
}
static INLINE void cnt_reset(int id)
{
    uint32_t reg;
    reg = RD_WORD(GLOBAL_REG_RESET_CTRL_4);
    uint32_t mask = 0x1UL << (4 + id);
    reg &= ~mask;
    WR_WORD(GLOBAL_REG_RESET_CTRL_4, reg);

    /* need 2 nop at least. */
    __NOP();
    __NOP();
    __NOP();
    __NOP();
    __NOP();

    WR_WORD(GLOBAL_REG_RESET_CTRL_4, reg | mask);
}

static INLINE void cnt_reset_pclk(void)
{
    uint32_t reg;
    reg = RD_WORD(GLOBAL_REG_RESET_CTRL_5);
    
    reg &= ~GLOBAL_REG_RESET_CTRL_5_CTL_RESET_5_D0_COUNTER_TOP_PCLK_RSTN_REG;
    WR_WORD(GLOBAL_REG_RESET_CTRL_4, reg);

    reg |= GLOBAL_REG_RESET_CTRL_5_CTL_RESET_5_D0_COUNTER_TOP_PCLK_RSTN_REG;
    WR_WORD(GLOBAL_REG_RESET_CTRL_4, reg);
}
static INLINE uint32_t cnt_snap_status(uint32_t base)
{
    return RD_WORD(COUNTER_ALL_APB_REG_SNAP_STATUS_C0 + base);
}
static INLINE uint32_t cnt_intr_status(void)
{
    return RD_WORD(COUNTER_ALL_APB_REG_INTR_STATUS);
}
static INLINE uint32_t cnt_intr_mask_status(void)
{
    return RD_WORD(COUNTER_ALL_APB_REG_INTR_MASK_STATUS);
}
static INLINE void cnt_intr_clear(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_INTR_CLR, val);
}
static INLINE void cnt_intr_set(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_INTR_SET, val);
}
static INLINE void cnt_intr_mask_set(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_INTR_MASK_SET, val);
}
static INLINE void cnt_intr_mask_clear(uint32_t val)
{
    WR_WORD(COUNTER_ALL_APB_REG_INTR_MASK_CLR, val);
}

static INLINE void cnt_intr_sw_reset()
{
    WR_WORD(COUNTER_ALL_APB_REG_INTR_SRESET, 1);
    WR_WORD(COUNTER_ALL_APB_REG_INTR_SRESET, 0);
}
static INLINE void cnt_trigger_global_start(void)
{
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_START_TRIGGER, 1);
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_START_TRIGGER, 0);
}
static INLINE void cnt_trigger_global_stop(void)
{
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_STOP_TRIGGER, 1);
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_STOP_TRIGGER, 0);
}
static INLINE void cnt_trigger_global_clear(void) // clear to 0x0
{
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_CLEAR_TRIGGER, 1);
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_CLEAR_TRIGGER, 0);
}
static INLINE void cnt_trigger_global_reset(void) // equal to stop + clear
{
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_RESET_TRIGGER, 1);
    WR_WORD(COUNTER_ALL_APB_REG_GLOBAL_RESET_TRIGGER, 0);
}
void cnt_resume(cnt_dev_t *pd);

cnt_dev_t* hal_cnt_open(int id, cnt_init_t *init);

void hal_cnt_close(cnt_dev_t* dev);

int hal_cnt_sync(cnt_dev_t* dev, uint32_t mask);

int hal_cnt_intr_mask(cnt_dev_t* dev);

int hal_cnt_intr_unmask(cnt_dev_t* dev);

int hal_cnt_pin_mux_en(int port, int pin, int en);

int hal_cnt_internal_din_pinmux(int inner_pin, int ext_port, int ext_pin);

int hal_cnt_internal_dout_pinmux(int inner_pin, int ext_port, int ext_pin);

int hal_cnt_enable(cnt_dev_t* dev);

int hal_cnt_disable(cnt_dev_t* dev);

uint32_t hal_cnt_get_clk(cnt_dev_t* dev);

int hal_cnt_pin_chk(int port, int pin);

void hal_cnt_set_handler(cnt_dev_t* dev, CNT_ISR_FUN fun, void* arg);


#endif