InPlay API
hal_audio.h
1 
13 #ifndef HAL_AUDIO_H
14 #define HAL_AUDIO_H
15 
24 #include "in_config.h"
25 #include <stdint.h>
26 #include <math.h>
27 #include "in_mmap.h"
28 #include "cmsis_os.h"
29 #include "./hal/hal_power.h"
30 /*
31  ****************************************************************************************
32  * Defines
33  ****************************************************************************************
34  */
35 #define AUD_INT_PKT_FIFO_OV_UDF 0x1
36 #define AUD_INT_DMA_FIFO_OV 0x2
37 #define AUD_INT_DMA_FIFO_UDF 0x4
38 #define AUD_INT_LAST_BYTE_ON_RIGHT 0x8
39 #define AUD_INT_DEC_INP_FIFO_OV_UDF 0x10
40 #define AUD_INT_PCM_FIFO_OV_UDF 0x20
41 #define AUD_INT_READ_GRANT 0x40
42 #define AUD_INT_READ_VALID 0x80
43 #define AUD_INT_OUT_FIFO_OV 0x100
44 #define AUD_INT_OUT_FIFO_UDF 0x200
45 #define AUD_INT_PPM_POS_SAT 0x400
46 #define AUD_INT_PPM_NEG_SAT 0x800
47 #define AUD_INT_ENC_READ_ADDR_OV 0x1000
48 #define AUD_INT_ENC_READ_ADDR_UDF 0x2000
49 #define AUD_INT_DEC_READ_ADDR_OV 0x4000
50 #define AUD_INT_DEC_READ_ADDR_UDF 0x8000
51 #define AUD_INT_TX_RD_SHM_PKT_FIFO_OV_UDF 0x10000
52 #define AUD_INT_TX_RD_SHM_DMA_FIFO_OV 0x20000
53 #define AUD_INT_TX_RD_SHM_DMA_FIFO_UDF 0x40000
54 #define AUD_INT_TX_WR_SHM_OUT_FIFO_UDF 0x80000
55 #define AUD_INT_TX_WR_SHM_DMA_FIFO_UDF 0x100000
56 #define AUD_INT_TX_WR_SHM_DMA_FIFO_OV 0x200000
57 #define AUD_INT_DEC_LMT_DATA 0x400000
58 #define AUD_INT_ENC_LMT_DATA 0x800000
59 
60 
61 /*
62  ****************************************************************************************
63  * INLINE FUNCTIONS
64  ****************************************************************************************
65  */
66 static __inline uint32_t audio_intr_status()
67 {
68  return RD_WORD(AUDIO_REGS_INTR_STATUS);
69 }
70 
71 static __inline void audio_intr_clear(uint32_t val)
72 {
73  WR_WORD(AUDIO_REGS_INTR_CLEAR, (val & AUDIO_REGS_INTR_MASK_CLEAR_INTR_MASK));
74 }
75 
76 static __inline void audio_intr_mask_set(uint32_t val)
77 {
78  WR_WORD(AUDIO_REGS_INTR_MASK_SET, (val & AUDIO_REGS_INTR_MASK_SET_INTR_MASK));
79 }
80 
81 static __inline void audio_intr_mask_clear(uint32_t val)
82 {
83  WR_WORD(AUDIO_REGS_INTR_MASK_CLEAR, (val & AUDIO_REGS_INTR_MASK_CLEAR_INTR_MASK));
84 }
85 
86 static __inline void audio_aenc_sreset()
87 {
88  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
89  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AURX_SRESET;
90  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
91  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_AURX_SRESET;
92  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
93 }
94 
95 static __inline void audio_aenc_enable()
96 {
97  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
98  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AENC_EN;
99  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
100 }
101 
102 static __inline void audio_aenc_disable()
103 {
104  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
105  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_AENC_EN;
106  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
107 }
108 
109 static __inline void audio_aenc_restart()
110 {
111  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
112  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AENC_RESTART;
113  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
114  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_AENC_RESTART;
115  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
116 }
117 
118 static __inline void audio_dec_enable()
119 {
120  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
121  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_ADEC_EN;
122  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
123 }
124 
125 static __inline void audio_dec_disable()
126 {
127  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
128  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_ADEC_EN;
129  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
130 }
131 
132 static __inline void audio_dec_restart()
133 {
134  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
135  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_ADEC_RESTART;
136  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
137  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_ADEC_RESTART;
138  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
139 }
140 
141 static __inline void audio_autx_reset()
142 {
143  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
144  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SRESET;
145  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
146  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SRESET;
147  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
148 }
149 static __inline void audio_autx_reset_spk()
150 {
151  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
152  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SRESET_SPK;
153  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
154  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SRESET_SPK;
155  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
156 }
157 
158 static __inline void audio_tx_out_enable()
159 {
160  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
161  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_OUT_EN;
162  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
163 }
164 
165 static __inline void audio_tx_out_disable()
166 {
167  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
168  reg &= ~(AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_OUT_EN);
169  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
170 }
171 
172 static __inline void audio_afifo_en_wr_enable()
173 {
174  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
175  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_AFIFO_EN_WR;
176  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
177 }
178 
179 static __inline void audio_afifo_en_wr_disable()
180 {
181  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
182  reg &= ~(AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_AFIFO_EN_WR);
183  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
184 }
185 
186 static __inline void audio_afifo_en_rd_enable()
187 {
188  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
189  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_AFIFO_EN_RD;
190  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
191 }
192 
193 static __inline void audio_afifo_en_rd_disable()
194 {
195  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
196  reg &= ~(AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_AFIFO_EN_RD);
197  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
198 }
199 
200 static __inline void audio_autx_sdm_enable()
201 {
202  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
203  reg |= (AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SDM_EN);
204  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
205 }
206 
207 static __inline void audio_autx_sdm_disable()
208 {
209  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
210  reg &= ~(AUDIO_REGS_MISC_CTRL0_CTLT_AUTX_SDM_EN);
211  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
212 }
213 
214 static __inline void audio_rx_stereo_enable()
215 {
216  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
217  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_AURX_STEREO;
218  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
219 }
220 
221 static __inline void audio_rx_stereo_disable()
222 {
223  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
224  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_AURX_STEREO;
225  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
226 }
227 
228 static __inline void audio_aenc_stereo_enable()
229 {
230  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
231  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_AENC_STEREO;
232  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
233 }
234 
235 static __inline void audio_aenc_stereo_disable()
236 {
237  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
238  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_AENC_STEREO;
239  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
240 }
241 
242 static __inline uint8_t audio_get_aenc_audio_mode()
243 {
244  return ((RD_WORD(AUDIO_REGS_MISC_CTRL0) & AUDIO_REGS_MISC_CTRL0_CTLQ_AENC_STEREO) > 0) ? 1 : 0;
245 }
246 
247 static __inline void audio_adec_stereo_enable()
248 {
249  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
250  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_ADEC_STEREO;
251  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
252 }
253 
254 static __inline void audio_adec_stereo_disable()
255 {
256  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
257  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_ADEC_STEREO;
258  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
259 }
260 
261 static __inline uint8_t audio_get_adec_audio_mode()
262 {
263  return ((RD_WORD(AUDIO_REGS_MISC_CTRL0) & AUDIO_REGS_MISC_CTRL0_CTLQ_ADEC_STEREO) > 0) ? 1 : 0;
264 }
265 
266 static __inline void audio_tx_stereo_enable()
267 {
268  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
269  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_STEREO;
270  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
271 }
272 
273 static __inline void audio_tx_stereo_disable()
274 {
275  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
276  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_STEREO;
277  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
278 }
279 
280 static __inline void audio_tx_i2s_master_enable()
281 {
282  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
283  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_I2SM_SEL;
284  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
285 }
286 
287 static __inline void audio_tx_i2s_master_disable()
288 {
289  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
290  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_I2SM_SEL;
291  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
292 }
293 
294 static __inline void audio_tx_i2s_slave_enable()
295 {
296  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
297  reg |= AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_I2SS_SEL;
298  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
299 }
300 
301 static __inline void audio_tx_i2s_slave_disable()
302 {
303  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
304  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLQ_AUTX_I2SS_SEL;
305  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
306 }
307 
308 static __inline void audio_rx_pdm_enable()
309 {
310  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
311  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_PDM_EN;
312  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
313 }
314 
315 static __inline void audio_rx_pdm_disable()
316 {
317  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
318  reg &= ~AUDIO_REGS_MISC_CTRL0_CTLT_PDM_EN;
319  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
320 }
321 
322 static __inline void audio_rx_pdm_clk_enable()
323 {
324  uint32_t reg = RD_WORD(AUDIO_REGS_MISC_CTRL0);
325  reg |= AUDIO_REGS_MISC_CTRL0_CTLT_PDM_CLK_EN;
326  WR_WORD(AUDIO_REGS_MISC_CTRL0, reg);
327 }
328 
329 static __inline void audio_rx_i2s_byp_all_enable()
330 {
331  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
332  reg |= AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_BYP;
333  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
334 }
335 
336 static __inline void audio_rx_i2s_byp_all_disable()
337 {
338  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
339  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_BYP;
340  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
341 }
342 
343 static __inline void audio_rx_in_format_i2s()
344 {
345  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
346  reg |= AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_IN_FORMAT;
347  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
348 }
349 
350 static __inline void audio_rx_in_format_pdm()
351 {
352  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
353  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_IN_FORMAT;
354  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
355 }
356 
357 static __inline void audio_rx_set_cic_dec(uint8_t val)
358 {
359  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
360  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_DEC;
361  reg |= ((val & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_DEC_MASK) << AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_DEC_SHIFT);
362  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
363 }
364 
365 static __inline uint8_t audio_rx_get_cic_dec()
366 {
367  return ((RD_WORD(AUDIO_REGS_AURX_CTRL0) >> AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_DEC_SHIFT) & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_DEC_MASK);
368 }
369 
370 static __inline void audio_rx_set_dc_off(uint32_t val)
371 {
372  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
373  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_DC_OFF;
374  reg |= ((val & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_DC_OFF_MASK) << AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_DC_OFF_SHIFT);
375  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
376 }
377 
378 static __inline uint32_t audio_rx_get_dc_off()
379 {
380  return ((RD_WORD(AUDIO_REGS_AURX_CTRL0) >> AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_DC_OFF_SHIFT) & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_DC_OFF_MASK);
381 }
382 
383 static __inline void audio_rx_set_cic_shift(uint8_t val)
384 {
385  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
386  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_SHIFT;
387  reg |= ((val & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_SHIFT_MASK) << AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_SHIFT_SHIFT);
388  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
389 }
390 
391 static __inline uint8_t audio_rx_get_cic_shift()
392 {
393  return ((RD_WORD(AUDIO_REGS_AURX_CTRL0) >> AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_SHIFT_SHIFT) & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_CIC_SHIFT_MASK);
394 }
395 
396 static __inline void audio_rx_set_i2s_shift(uint8_t val)
397 {
398  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
399  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_SHIFT;
400  reg |= ((val & AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_SHIFT_MASK) << AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_SHIFT_SHIFT);
401  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
402 }
403 static __inline void audio_rx_pdm_cic_init(uint8_t audio_pdm_aurx_cic_dec, uint32_t audio_pdm_aurx_cic_dec_offset, uint8_t audio_pdm_aurx_cic_dec_shift)
404 {
405  audio_rx_set_cic_dec(audio_pdm_aurx_cic_dec);
406  audio_rx_set_dc_off(audio_pdm_aurx_cic_dec_offset);
407  audio_rx_set_cic_shift(audio_pdm_aurx_cic_dec_shift);
408 }
409 
410 static __inline void audio_rx_i2s_master_core()
411 {
412  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
413  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_SLAVE;
414  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
415 }
416 
417 static __inline void audio_rx_i2s_slave_core()
418 {
419  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
420  reg |= AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_SLAVE;
421  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
422 }
423 
424 static __inline void audio_rx_i2s_byp_ib4_db5_enable()
425 {
426  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
427  reg |= AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_D5;
428  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
429 }
430 
431 static __inline void audio_rx_i2s_byp_ib4_db5_disable()
432 {
433  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL0);
434  reg &= ~AUDIO_REGS_AURX_CTRL0_CTLQ_AURX_I2S_D5;
435  WR_WORD(AUDIO_REGS_AURX_CTRL0, reg);
436 }
437 
438 static __inline void audio_rx_set_itp_per(uint8_t val)
439 {
440  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
441  reg &= ~AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_ITP_PER;
442  reg |= ((val >> AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_ITP_PER_SHIFT) & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_ITP_PER_MASK);
443  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
444 }
445 
446 static __inline void audio_rx_lpf2_dec_execute()
447 {
448  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
449  reg |= AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_LPF2_DEC;
450  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
451 }
452 
453 static __inline void audio_rx_lpf2_dec_bypass()
454 {
455  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
456  reg &= ~AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_LPF2_DEC;
457  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
458 }
459 
460 static __inline void audio_rx_set_gain_left(uint16_t val)
461 {
462  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
463  reg &= ~AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINL;
464  reg |= ((val & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINL_MASK) << AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINL_SHIFT);
465  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
466 }
467 
468 static __inline uint16_t audio_rx_get_gain_left() {
469  return (RD_WORD(AUDIO_REGS_AURX_CTRL1) >> AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINL_SHIFT) & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINL_MASK;
470 }
471 
472 static __inline void audio_rx_set_gain_right(uint16_t val)
473 {
474  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
475  reg &= ~AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINR;
476  reg |= ((val & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINR_MASK) << AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINR_SHIFT);
477  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
478 }
479 
480 static __inline uint16_t audio_rx_get_gain_right() {
481  return (RD_WORD(AUDIO_REGS_AURX_CTRL1) >> AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINR_SHIFT) & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_GAINR_MASK;
482 }
483 
484 static __inline void audio_rx_set_i2s_delay(uint8_t val)
485 {
486  uint32_t reg = RD_WORD(AUDIO_REGS_AURX_CTRL1);
487  reg &= ~AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_I2S_DEL;
488  reg |= ((val & AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_I2S_DEL_MASK) << AUDIO_REGS_AURX_CTRL1_CTLQ_AURX_I2S_DEL_SHIFT);
489  WR_WORD(AUDIO_REGS_AURX_CTRL1, reg);
490 }
491 
492 static __inline void audio_rx_set_aenc_pkt_fifo_th(uint8_t thresh)
493 {
494  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
495  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PKT_FIFO_TH;
496  reg |= ((thresh >> AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PKT_FIFO_TH_SHIFT) & AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PKT_FIFO_TH_MASK);
497  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
498 }
499 
500 static __inline void audio_rx_set_aenc_num_samp_per_blk(uint16_t size)
501 {
502  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
503  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SIZE;
504  reg |= ((size & AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SIZE_MASK) << AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SIZE_SHIFT);
505  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
506 }
507 
508 static __inline void audio_rx_set_aenc_mode(uint8_t mode)
509 {
510  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
511  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_MODE;
512  reg |= ((mode & AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_MODE_MASK) << AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_MODE_SHIFT);
513  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
514 }
515 
516 static __inline void audio_rx_set_aenc_fsamppredic()
517 {
518  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
519  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_FSAMPPREDIC;
520  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
521 }
522 
523 static __inline void audio_rx_clr_aenc_fsamppredic()
524 {
525  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
526  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_FSAMPPREDIC;
527  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
528 }
529 
530 static __inline void audio_rx_set_aenc_skip_fsamp()
531 {
532  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
533  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SKIP_FSAMP;
534  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
535 }
536 
537 static __inline void audio_rx_clr_aenc_skip_fsamp()
538 {
539  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
540  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SKIP_FSAMP;
541  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
542 }
543 
544 static __inline uint8_t audio_rx_get_aenc_skip_fsamp()
545 {
546  return ((RD_WORD(AUDIO_REGS_AENC_CTRL0) & AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_SKIP_FSAMP) > 0) ? 1 : 0;
547 }
548 
549 static __inline uint16_t audio_rx_init_aenc_num_samp_per_blk(int num_bytes_per_frame, int stereo_mode)
550 {
551  uint16_t val;
552  if(stereo_mode)
553  val = ((num_bytes_per_frame/2 - 3) * 2) + audio_rx_get_aenc_skip_fsamp();
554  else
555  val = ((num_bytes_per_frame - 3) * 2) + audio_rx_get_aenc_skip_fsamp();
556  audio_rx_set_aenc_num_samp_per_blk(val);
557  return val;
558 }
559 
560 static __inline void audio_rx_set_aenc_predic_end()
561 {
562  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
563  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PREDIC_END;
564  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
565 }
566 
567 static __inline void audio_rx_clr_aenc_predic_end()
568 {
569  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
570  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PREDIC_END;
571  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
572 }
573 
574 static __inline uint8_t audio_rx_get_aenc_predic_end()
575 {
576  return ((RD_WORD(AUDIO_REGS_AENC_CTRL0) & AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_PREDIC_END) > 0) ? 1 : 0;
577 }
578 
579 static __inline void audio_rx_set_aenc_lsb4first()
580 {
581  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
582  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_LSB4FIRST;
583  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
584 }
585 
586 static __inline void audio_rx_clr_aenc_lsb4first()
587 {
588  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
589  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_LSB4FIRST;
590  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
591 }
592 
593 static __inline void audio_rx_set_aenc_applepredic()
594 {
595  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
596  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_APPLEPREDIC;
597  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
598 }
599 
600 static __inline void audio_rx_clr_aenc_applepredic()
601 {
602  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
603  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_APPLEPREDIC;
604  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
605 }
606 
607 static __inline void audio_rx_set_aenc_rst_stepidx()
608 {
609  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
610  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_RST_STEPIDX;
611  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
612 }
613 
614 static __inline void audio_rx_clr_aenc_rst_stepidx()
615 {
616  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
617  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_RST_STEPIDX;
618  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
619 }
620 
621 static __inline void audio_rx_set_aenc_rst_predict()
622 {
623  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
624  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_RST_PREDICT;
625  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
626 }
627 
628 static __inline void audio_rx_clr_aenc_rst_predict()
629 {
630  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
631  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_RST_PREDICT;
632  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
633 }
634 
635 static __inline void audio_rx_set_aenc_wr_priority()
636 {
637  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
638  reg |= AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_WR_PRIORITY;
639  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
640 }
641 
642 static __inline void audio_rx_clr_aenc_wr_priority()
643 {
644  uint32_t reg = RD_WORD(AUDIO_REGS_AENC_CTRL0);
645  reg &= ~AUDIO_REGS_AENC_CTRL0_CTLQ_AENC_WR_PRIORITY;
646  WR_WORD(AUDIO_REGS_AENC_CTRL0, reg);
647 }
648 
649 static __inline void audio_rx_set_aenc_max_addr(uint32_t max_addr)
650 {
651  WR_WORD(AUDIO_REGS_AENC_CTRL1, ((max_addr - 1) & 0x7FF));
652 }
653 
654 static __inline uint8_t audio_get_aenc_dma_fifo_rptr()
655 {
656  return ((RD_WORD(AUDIO_REGS_AENC_STAT0) >> AUDIO_REGS_AENC_STAT0_STS_AENC_DMA_FIFO_RPTR_SHIFT) & AUDIO_REGS_AENC_STAT0_STS_AENC_DMA_FIFO_RPTR_MASK);
657 }
658 
659 static __inline uint8_t audio_get_aenc_dma_fifo_wptr()
660 {
661  return ((RD_WORD(AUDIO_REGS_AENC_STAT0) >> AUDIO_REGS_AENC_STAT0_STS_AENC_DMA_FIFO_WPTR_SHIFT) & AUDIO_REGS_AENC_STAT0_STS_AENC_DMA_FIFO_WPTR_MASK);
662 }
663 
664 static __inline void audio_tx_set_adec_num_samp_per_blk(uint16_t size)
665 {
666  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
667  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_SIZE;
668  reg |= ((size & AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_SIZE_MASK) >> AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_SIZE_SHIFT);
669  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
670 }
671 
672 static __inline void audio_tx_set_adec_mode(uint8_t mode)
673 {
674  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
675  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MODE;
676  reg |= ((mode & AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MODE_MASK) << AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MODE_SHIFT);
677  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
678 }
679 
680 static __inline void audio_tx_set_adec_predicfsamp()
681 {
682  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
683  reg |= AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_PREDICFSAMP;
684  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
685 }
686 
687 static __inline void audio_tx_clr_adec_predicfsamp()
688 {
689  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
690  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_PREDICFSAMP;
691  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
692 }
693 
694 static __inline uint8_t audio_tx_get_adec_predicfsamp()
695 {
696  return ((RD_WORD(AUDIO_REGS_ADEC_CTRL0) & AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_PREDICFSAMP) > 0) ? 1 : 0;
697 }
698 
699 static __inline uint16_t audio_tx_init_adec_num_samp_per_blk(int num_bytes_per_frame, int stereo_mode)
700 {
701  uint16_t val;
702  if(stereo_mode)
703  val = ((num_bytes_per_frame/2 - 3) * 2) + audio_tx_get_adec_predicfsamp();
704  else
705  val = (num_bytes_per_frame - 3) + audio_tx_get_adec_predicfsamp();
706 
707  audio_tx_set_adec_num_samp_per_blk(val);
708  return val;
709 }
710 
711 static __inline void audio_tx_set_adec_predic_end()
712 {
713  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
714  reg |= AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_PREDIC_END;
715  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
716 }
717 
718 static __inline void audio_tx_clr_adec_predic_end()
719 {
720  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
721  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_PREDIC_END;
722  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
723 }
724 
725 static __inline void audio_tx_set_adec_lsb4first()
726 {
727  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
728  reg |= AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_LSB4FIRST;
729  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
730 }
731 
732 static __inline void audio_tx_clr_adec_lsb4first()
733 {
734  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
735  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_LSB4FIRST;
736  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
737 }
738 
739 static __inline void audio_tx_set_adec_rst_stepidx()
740 {
741  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
742  reg |= AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_RST_STEPIDX;
743  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
744 }
745 
746 static __inline void audio_tx_clr_adec_rst_stepidx()
747 {
748  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
749  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_RST_STEPIDX;
750  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
751 }
752 
753 static __inline void audio_tx_set_adec_rst_predict()
754 {
755  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
756  reg |= AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_RST_PREDICT;
757  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
758 }
759 
760 static __inline void audio_tx_clr_adec_rst_predict()
761 {
762  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
763  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_RST_PREDICT;
764  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
765 }
766 
767 static __inline void audio_tx_set_adec_max_addr(uint32_t max_addr)
768 {
769  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_CTRL0);
770  reg &= ~AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MAX_ADDR;
771  reg |= (((max_addr-1) & AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MAX_ADDR_MASK) << AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MAX_ADDR_SHIFT);
772  WR_WORD(AUDIO_REGS_ADEC_CTRL0, reg);
773 }
774 
775 static __inline uint16_t audio_tx_get_adec_max_addr()
776 {
777  return ((RD_WORD(AUDIO_REGS_ADEC_CTRL0) >> AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MAX_ADDR_SHIFT) & AUDIO_REGS_ADEC_CTRL0_CTLQ_ADEC_MAX_ADDR_MASK);
778 }
779 
780 static __inline void audio_tx_bypass_itpto32_lpf_enable()
781 {
782  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
783  reg |= AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_BYP_LPF;
784  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
785 }
786 
787 static __inline void audio_tx_bypass_itpto32_lpf_disable()
788 {
789  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
790  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_BYP_LPF;
791  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
792 }
793 
794 static __inline void audio_tx_bypass_itpto32_up2_enable()
795 {
796  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
797  reg |= AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_BYP_UP2;
798  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
799 }
800 
801 static __inline void audio_tx_bypass_itpto32_up2_disable()
802 {
803  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
804  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_BYP_UP2;
805  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
806 }
807 
808 static __inline void audio_tx_set_itpto32_per(uint16_t val)
809 {
810  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
811  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_PER;
812  reg |= ((val & AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_PER_MASK) << AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO32_PER_SHIFT);
813  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
814 }
815 
816 static __inline void audio_tx_bypass_itpto64_lpf_enable()
817 {
818  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
819  reg |= AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO64_BYP_LPF;
820  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
821 }
822 
823 static __inline void audio_tx_bypass_itpto64_lpf_disable()
824 {
825  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
826  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO64_BYP_LPF;
827  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
828 }
829 
830 static __inline void audio_tx_set_itpto64_per(uint16_t val)
831 {
832  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
833  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO64_PER;
834  reg |= ((val & AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO64_PER_MASK) << AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO64_PER_SHIFT);
835  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
836 }
837 
838 static __inline void audio_tx_bypass_itpto128_lpf_enable()
839 {
840  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
841  reg |= AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO128_BYP_LPF;
842  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
843 }
844 
845 static __inline void audio_tx_bypass_itpto128_lpf_disable()
846 {
847  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
848  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO128_BYP_LPF;
849  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
850 }
851 
852 static __inline void audio_tx_set_itpto128_per(uint16_t val)
853 {
854  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
855  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO128_PER;
856  reg |= ((val & AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO128_PER_MASK) << AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_ITPTO128_PER_SHIFT);
857  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
858 }
859 
860 static __inline void audio_tx_set_audio_tx_in_dma_sharedmem()
861 {
862  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
863  reg |= AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_SEL_IN;
864  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
865 }
866 
867 static __inline void audio_tx_set_audio_tx_in_adpcm()
868 {
869  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL0);
870  reg &= ~AUDIO_REGS_AUTX_CTRL0_CTLQ_AUTX_SEL_IN;
871  WR_WORD(AUDIO_REGS_AUTX_CTRL0, reg);
872 }
873 
874 static __inline void audio_tx_set_vid_nomrate(uint32_t val)
875 {
876  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL1);
877  reg &= ~AUDIO_REGS_AUTX_CTRL1_CTLQ_AUTX_VID_NOMRATE;
878  reg |= ((val & AUDIO_REGS_AUTX_CTRL1_CTLQ_AUTX_VID_NOMRATE_MASK) << AUDIO_REGS_AUTX_CTRL1_CTLQ_AUTX_VID_NOMRATE_SHIFT);
879  WR_WORD(AUDIO_REGS_AUTX_CTRL1, reg);
880 }
881 
882 static __inline void audio_tx_set_vid_invrate(uint16_t val)
883 {
884  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL2);
885  reg &= ~AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_VID_INVRATE;
886  reg |= ((val & AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_VID_INVRATE_MASK) << AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_VID_INVRATE_SHIFT);
887  WR_WORD(AUDIO_REGS_AUTX_CTRL2, reg);
888 }
889 
890 static __inline void audio_tx_set_gainr(uint16_t val)
891 {
892  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL2);
893  reg &= ~AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_GAINR;
894  reg |= ((val & AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_GAINR_MASK) << AUDIO_REGS_AUTX_CTRL2_CTLQ_AUTX_GAINR_SHIFT);
895  WR_WORD(AUDIO_REGS_AUTX_CTRL2, reg);
896 }
897 
898 static __inline void audio_tx_set_out_per(uint8_t val)
899 {
900  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL3);
901  reg &= ~AUDIO_REGS_AUTX_CTRL3_CTLT_AUTX_OUT_PER;
902  reg |= ((val & AUDIO_REGS_AUTX_CTRL3_CTLT_AUTX_OUT_PER_MASK) << AUDIO_REGS_AUTX_CTRL3_CTLT_AUTX_OUT_PER_SHIFT);
903  WR_WORD(AUDIO_REGS_AUTX_CTRL3, reg);
904 }
905 
906 static __inline void audio_tx_set_gainl(uint16_t val)
907 {
908  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_CTRL3);
909  reg &= ~AUDIO_REGS_AUTX_CTRL3_CTLQ_AUTX_GAINL;
910  reg |= ((val & AUDIO_REGS_AUTX_CTRL3_CTLQ_AUTX_GAINL_MASK) << AUDIO_REGS_AUTX_CTRL3_CTLQ_AUTX_GAINL_SHIFT);
911  WR_WORD(AUDIO_REGS_AUTX_CTRL3, reg);
912 }
913 
914 static __inline void audio_tx_set_adec_pcm_freq_den(uint16_t val)
915 {
916  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_RATE_CTRL0);
917  reg &= ~AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_DEN;
918  reg |= ((val & AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_DEN_MASK) << AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_DEN_SHIFT);
919  WR_WORD(AUDIO_REGS_ADEC_RATE_CTRL0, reg);
920 }
921 
922 static __inline void audio_tx_set_adec_pcm_freq_num(uint16_t val)
923 {
924  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_RATE_CTRL0);
925  reg &= ~AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_NUM;
926  reg |= ((val & AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_NUM_MASK) << AUDIO_REGS_ADEC_RATE_CTRL0_CTLQ_ADEC_PCM_FREQ_NUM_SHIFT);
927  WR_WORD(AUDIO_REGS_ADEC_RATE_CTRL0, reg);
928 }
929 
930 static __inline void audio_rx_enable_rd_dma_ack()
931 {
932  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_DMA_CTRL0);
933  reg |= AUDIO_REGS_ADEC_DMA_CTRL0_CTLQ_REG_DMA_RD_ACK;
934  WR_WORD(AUDIO_REGS_ADEC_DMA_CTRL0, reg);
935 }
936 
937 static __inline void audio_rx_disable_rd_dma_ack()
938 {
939  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_DMA_CTRL0);
940  reg &= ~AUDIO_REGS_ADEC_DMA_CTRL0_CTLQ_REG_DMA_RD_ACK;
941  WR_WORD(AUDIO_REGS_ADEC_DMA_CTRL0, reg);
942 }
943 
944 static __inline void audio_tx_enable_wr_dma_ack()
945 {
946  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_DMA_CTRL0);
947  reg |= AUDIO_REGS_ADEC_DMA_CTRL0_CTLQ_REG_DMA_WR_ACK;
948  WR_WORD(AUDIO_REGS_ADEC_DMA_CTRL0, reg);
949 }
950 
951 static __inline void audio_tx_disable_wr_dma_ack()
952 {
953  uint32_t reg = RD_WORD(AUDIO_REGS_ADEC_DMA_CTRL0);
954  reg &= ~AUDIO_REGS_ADEC_DMA_CTRL0_CTLQ_REG_DMA_WR_ACK;
955  WR_WORD(AUDIO_REGS_ADEC_DMA_CTRL0, reg);
956 }
957 
958 static __inline uint16_t audio_get_adec_bytes_in_ram()
959 {
960  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) & AUDIO_REGS_ADEC_DMA_STAT0_STS_ADEC_BYTES_IN_RAM));
961 }
962 
963 static __inline uint16_t audio_get_aenc_dma_rd_req()
964 {
965  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) & AUDIO_REGS_ADEC_DMA_STAT0_STS_AENC_DMA_RD_REQ) > 0) ? 1 : 0;
966 }
967 
968 static __inline uint8_t audio_get_adec_dma_fifo_full()
969 {
970  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) & AUDIO_REGS_ADEC_DMA_STAT0_STS_ADEC_DMA_FIFO_FULL) > 0) ? 1 : 0;
971 }
972 
973 static __inline uint16_t audio_get_aenc_bytes_in_ram()
974 {
975  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) >> AUDIO_REGS_ADEC_DMA_STAT0_STS_AENC_BYTES_IN_RAM_SHIFT) & AUDIO_REGS_ADEC_DMA_STAT0_STS_AENC_BYTES_IN_RAM_MASK);
976 }
977 
978 static __inline uint16_t audio_get_adec_dma_wr_req()
979 {
980  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) & AUDIO_REGS_ADEC_DMA_STAT0_STS_ADEC_DMA_WR_REQ) > 0) ? 1 : 0;
981 }
982 
983 static __inline uint8_t audio_get_aenc_dma_fifo_full()
984 {
985  return ((RD_WORD(AUDIO_REGS_ADEC_DMA_STAT0) & AUDIO_REGS_ADEC_DMA_STAT0_STS_AENC_DMA_FIFO_FULL) > 0) ? 1 : 0;
986 }
987 
988 static __inline uint32_t audio_rx_dma_read()
989 {
990  return RD_WORD(AUDIO_REGS_DMA_READ);
991 }
992 
993 static __inline void audio_tx_dma_write(uint32_t data)
994 {
995  WR_WORD(AUDIO_REGS_ADEC_DMA_WRITE, data);
996 }
997 
998 static __inline void audio_rx_pdm_init_clk0(uint8_t pdm_clk_period, uint8_t l_high_sample, uint8_t r_high_sample)
999 {
1000  uint32_t reg = 0;
1001  reg |= pdm_clk_period - 1;
1002  if (pdm_clk_period != 2)
1003  reg |= ((pdm_clk_period/2 + 1) << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_FALL_SHIFT);
1004  uint32_t val = pdm_clk_period / 4;
1005  uint8_t x = 0xFF;
1006  reg &= ~(x << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_LCNT_SHIFT);
1007  reg &= ~(x << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_RCNT_SHIFT);
1008  if(l_high_sample)
1009  reg |= ((val) << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_LCNT_SHIFT);
1010  else
1011  reg |= ((val*3) << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_LCNT_SHIFT);
1012 
1013 
1014  if (r_high_sample)
1015  reg |= ((val) << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_RCNT_SHIFT);
1016  else
1017  reg |= ((val * 3) << AUDIO_REGS_PDM_CTRL0_CTLQ_PDM_RCNT_SHIFT);
1018 
1019  WR_WORD(AUDIO_REGS_PDM_CTRL0, reg);
1020 }
1021 
1022 static __inline void audio_rx_pdm_init_clk1(uint8_t audio_pdm_clk_period, uint8_t pdm_l_core, uint8_t pdm_r_core)
1023 {
1024  uint32_t reg = (audio_pdm_clk_period-4) | (uint32_t) (pdm_l_core << 8) | (uint32_t)(pdm_l_core << 9);
1025  WR_WORD(AUDIO_REGS_PDM_CTRL1, reg);
1026 }
1027 
1028 static __inline void audio_rdsm_dma_sel_audiotx()
1029 {
1030  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0);
1031  reg |= AUDIO_REGS_AUTX_SM_CTRL0_CTLQ_SM_DMA_RD_SEL;
1032  WR_WORD(AUDIO_REGS_AUTX_SM_CTRL0, reg);
1033 }
1034 
1035 static __inline void audio_rdsm_dma_sel_adpcm()
1036 {
1037  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0);
1038  reg &= ~AUDIO_REGS_AUTX_SM_CTRL0_CTLQ_SM_DMA_RD_SEL;
1039  WR_WORD(AUDIO_REGS_AUTX_SM_CTRL0, reg);
1040 }
1041 
1042 static __inline void audio_rdsm_autx_enable()
1043 {
1044  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0);
1045  reg |= AUDIO_REGS_AUTX_SM_CTRL0_CTLT_AUTX_SM_EN;
1046  WR_WORD(AUDIO_REGS_AUTX_SM_CTRL0, reg);
1047 }
1048 
1049 static __inline void audio_rdsm_autx_disable()
1050 {
1051  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0);
1052  reg &= ~AUDIO_REGS_AUTX_SM_CTRL0_CTLT_AUTX_SM_EN;
1053  WR_WORD(AUDIO_REGS_AUTX_SM_CTRL0, reg);
1054 }
1055 
1056 static __inline void audio_rdsm_set_max_addr()
1057 {
1058  uint16_t val = (CFG_SMEM_AUDIO_RX & 0xFFF) / 4;
1059  if(val >= 0x800)
1060  val = 0x7FF;
1061 
1062  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0);
1063  reg &= ~AUDIO_REGS_AUTX_SM_CTRL0_CTLQ_AUTX_MAX_ADDR;
1064  WR_WORD(AUDIO_REGS_AUTX_SM_CTRL0, val);
1065 }
1066 
1067 static __inline uint16_t audio_rdsm_get_max_addr()
1068 {
1069  return ((RD_WORD(AUDIO_REGS_AUTX_SM_CTRL0) >> AUDIO_REGS_AUTX_SM_CTRL0_CTLQ_AUTX_MAX_ADDR_SHIFT) & AUDIO_REGS_AUTX_SM_CTRL0_CTLQ_AUTX_MAX_ADDR_MASK);
1070 }
1071 
1072 static __inline uint16_t audio_rdsm_get_rd_buf_samps()
1073 {
1074  return ((RD_WORD(AUDIO_REGS_AUTX_SM_STAT0) >> AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_RD_BUF_SAMPS_SHIFT) & AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_RD_BUF_SAMPS_MASK);
1075 }
1076 
1077 static __inline uint16_t audio_rdsm_get_pkt_fifo_fill()
1078 {
1079  return ((RD_WORD(AUDIO_REGS_AUTX_SM_STAT0) >> AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_PKT_FIFO_FILL_SHIFT) & AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_PKT_FIFO_FILL_MASK);
1080 }
1081 
1082 static __inline uint16_t audio_rdsm_get_dma_fifo_fill()
1083 {
1084  return ((RD_WORD(AUDIO_REGS_AUTX_SM_STAT0) >> AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_DMA_FIFO_FILL_SHIFT) & AUDIO_REGS_AUTX_SM_STAT0_STS_AUTX_DMA_FIFO_FILL_MASK);
1085 }
1086 
1087 static __inline void audio_wrsm_dma_sel_audiotx()
1088 {
1089  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1090  reg |= AUDIO_REGS_AUTX_WRSM_CTRL0_CTLQ_SM_DMA_WR_SEL;
1091  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1092 }
1093 
1094 static __inline void audio_wrsm_dma_sel_adpcm()
1095 {
1096  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1097  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL0_CTLQ_SM_DMA_WR_SEL;
1098  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1099 }
1100 
1101 static __inline void audio_wrsm_autx_enable()
1102 {
1103  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1104  reg |= AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_EN;
1105  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1106 }
1107 
1108 static __inline void audio_wrsm_autx_disable()
1109 {
1110  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1111  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_EN;
1112  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1113 }
1114 
1115 static __inline void audio_wrsm_autx_pull_enable()
1116 {
1117  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1118  reg |= AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_PULL_EN;
1119  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1120 }
1121 
1122 static __inline void audio_wrsm_autx_pull_disable()
1123 {
1124  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1125  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_PULL_EN;
1126  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, reg);
1127 }
1128 
1129 static __inline void audio_wrsm_set_max_addr()
1130 {
1131  uint16_t val = (CFG_SMEM_AUDIO_TX & 0xFFF) / 4;
1132  if(val >= 0x800)
1133  val = 0x7FF;
1134 
1135  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0);
1136  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_MAX_ADDR;
1137  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0, val);
1138 }
1139 
1140 static __inline uint16_t audio_wrsm_get_max_addr()
1141 {
1142  return ((RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL0) >> AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_MAX_ADDR_SHIFT) & AUDIO_REGS_AUTX_WRSM_CTRL0_CTLT_WRSM_MAX_ADDR_MASK);
1143 }
1144 
1145 static __inline void audio_wrsm_set_pull_den(uint16_t val)
1146 {
1147  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL1);
1148  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_DEN;
1149  reg |= ((val & AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_DEN_MASK) << AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_DEN_SHIFT);
1150  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL1, reg);
1151 }
1152 
1153 static __inline void audio_wrsm_set_pull_num(uint16_t val)
1154 {
1155  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_WRSM_CTRL1);
1156  reg &= ~AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_NUM;
1157  reg |= ((val & AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_NUM_MASK) << AUDIO_REGS_AUTX_WRSM_CTRL1_CTLQ_WRSM_PULL_NUM_SHIFT);
1158  WR_WORD(AUDIO_REGS_AUTX_WRSM_CTRL1, reg);
1159 }
1160 
1161 static __inline uint16_t audio_wrsm_get_wr_buf_samps()
1162 {
1163  return ((RD_WORD(AUDIO_REGS_AUTX_WRSM_STAT0) >> AUDIO_REGS_AUTX_WRSM_STAT0_STS_AUTX_WR_BUF_SAMPS_SHIFT) & AUDIO_REGS_AUTX_WRSM_STAT0_STS_AUTX_WR_BUF_SAMPS_MASK);
1164 }
1165 
1166 static __inline uint16_t audio_wrsm_get_dmafifo_wfill()
1167 {
1168  return ((RD_WORD(AUDIO_REGS_AUTX_WRSM_STAT0) >> AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_DMAFIFO_WFILL_SHIFT) & AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_DMAFIFO_WFILL_MASK);
1169 }
1170 
1171 static __inline uint16_t audio_wrsm_get_outfifo_fill()
1172 {
1173  return ((RD_WORD(AUDIO_REGS_AUTX_WRSM_STAT0) >> AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_OUTFIFO_FILL_SHIFT) & AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_OUTFIFO_FILL_MASK);
1174 }
1175 
1176 static __inline uint16_t audio_wrsm_get_samps_in_mem()
1177 {
1178  return ((RD_WORD(AUDIO_REGS_AUTX_WRSM_STAT0) >> AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_SAMPS_IN_MEM_SHIFT) & AUDIO_REGS_AUTX_WRSM_STAT0_STS_WRSM_SAMPS_IN_MEM_MASK);
1179 }
1180 
1181 static __inline void audio_enc_ready_lmt(uint16_t limit)
1182 {
1183  WR_WORD(AUDIO_REGS_ENCODER_RDY_CONTROL, (limit & AUDIO_REGS_ENCODER_RDY_CONTROL_CTL_ENC_RDY_IRQ_LMT_MASK));
1184 }
1185 
1186 static __inline uint16_t audio_enc_ready_cnt(void)
1187 {
1188  return ((RD_WORD(AUDIO_REGS_ENCODER_RDY_CONTROL) & AUDIO_REGS_ENCODER_RDY_CONTROL_STS_CURR_ENC_RDY_CNT) >> AUDIO_REGS_ENCODER_RDY_CONTROL_STS_CURR_ENC_RDY_CNT_SHIFT);
1189 }
1190 
1191 
1192 static __inline void audio_dec_ready_lmt(uint16_t limit)
1193 {
1194  WR_WORD(AUDIO_REGS_DECODER_RDY_CONTROL, (limit & AUDIO_REGS_DECODER_RDY_CONTROL_CTL_DEC_RDY_IRQ_LMT_MASK));
1195 }
1196 
1197 static __inline uint16_t audio_dec_ready_cnt(void)
1198 {
1199  return ((RD_WORD(AUDIO_REGS_DECODER_RDY_CONTROL) & AUDIO_REGS_DECODER_RDY_CONTROL_STS_CURR_DEC_RDY_CNT) >> AUDIO_REGS_DECODER_RDY_CONTROL_STS_CURR_DEC_RDY_CNT_SHIFT);
1200 }
1201 
1202 static __inline void audio_tx_sdm_mod_index(uint8_t index)
1203 {
1204  uint32_t reg = RD_WORD(AUDIO_REGS_AUTX_SDM_CTRL0);
1205  reg &= ~AUDIO_REGS_AUTX_SDM_CTRL0_CTLQ_AUTX_SDM_MOD_INDEX;
1206  reg |= (index&AUDIO_REGS_AUTX_SDM_CTRL0_CTLQ_AUTX_SDM_MOD_INDEX_MASK) << AUDIO_REGS_AUTX_SDM_CTRL0_CTLQ_AUTX_SDM_MOD_INDEX_SHIFT;
1207  WR_WORD(AUDIO_REGS_AUTX_SDM_CTRL0, reg);
1208 }
1209 
1210 
1211 /*
1212  ****************************************************************************************
1213  * IMPLEMENTATION
1214  ****************************************************************************************
1215  */
1216 
1218 typedef enum {
1237 } audio_status_t;
1238 
1239 
1240 // DEFAULT INITIALIZATION
1248 int hal_audio_enc_open(void);
1249 
1257 int hal_audio_dec_open(void);
1258 
1266 int hal_audio_resample_open(void);
1267 
1275 int hal_audio_enc_close(void);
1276 
1284 int hal_audio_dec_close(void);
1285 
1293 int hal_audio_resample_close(void);
1294 
1295 // CONFIGURATION SET
1307 int hal_audio_enc_set_pdm_mic_inp(int pdm_l_core, int pdm_r_core, int wss_l_low);
1308 
1318 int hal_audio_enc_set_predict_endianness(int is_little_end);
1319 
1329 int hal_audio_dec_set_predict_endianness(int is_little_end);
1330 
1346 int hal_audio_enc_set_config(int is_pdm, int is_I2S_master, float in_rate, float out_rate, int is_stereo, int bytes_per_frame, int gain);
1366 int hal_audio_dec_set_config(int is_i2s, int is_I2S_master, float in_rate, float out_rate, uint8_t out_clk_src, float out_clk_rate, int is_stereo, int bytes_per_frame, int gain);
1367 
1380 int hal_audio_resample_set_config(float in_rate, float out_rate, int is_stereo, int gain);
1381 
1394 int hal_audio_resample_set_config(float in_rate, float out_rate, int is_stereo, int gain);
1395 
1409 int hal_audio_enc_pdm_dc_offset_cal(int bytes_per_frame, int is_stereo, int num_frames_skip, int num_frames_samp);
1410 
1411 // START
1419 int hal_audio_encode_start(void *pv, void (*enc_lmt_callback)(void *));
1420 
1433 int hal_audio_encode_process(uint8_t* out_buf, uint32_t buf_sz, uint16_t* in_size);
1434 int hal_audio_encode_read(uint8_t* out_buf, uint32_t buf_sz, uint16_t *in_size) ;
1435 
1436 
1448 int hal_audio_decode_start(uint8_t* in_buf, uint16_t buf_size, uint16_t* in_size, void *pv, void(*dec_lmt_callback)(void *pv));
1449 
1450 
1463 int hal_audio_decode_process(uint8_t* in_buf, uint16_t buf_size, uint16_t* in_size);
1464 int hal_audio_decode_write(uint8_t *in_buf, uint16_t buf_size, uint16_t *in_size) ;
1465 
1477 int hal_audio_resample_process(uint32_t* in_buf, uint16_t* in_size, uint32_t* out_buf);
1478 
1479 // STOP
1487 int hal_audio_encode_stop(void);
1488 
1496 int hal_audio_decode_stop(void);
1497 
1505 int hal_audio_resample_stop(void);
1507 #endif
1508 
1509 
int hal_audio_enc_set_pdm_mic_inp(int pdm_l_core, int pdm_r_core, int wss_l_low)
Configure PDM mic input control.
int hal_audio_enc_set_config(int is_pdm, int is_I2S_master, float in_rate, float out_rate, int is_stereo, int bytes_per_frame, int gain)
Configure audio_control encode function settings.
int hal_audio_encode_stop(void)
Stop encode audio functionality.
No error. Good status.
Definition: hal_audio.h:1220
int hal_audio_decode_stop(void)
Stop decode audio functionality.
int hal_audio_dec_set_config(int is_i2s, int is_I2S_master, float in_rate, float out_rate, uint8_t out_clk_src, float out_clk_rate, int is_stereo, int bytes_per_frame, int gain)
Configure audio_control decode function settings.
audio_status_t
Audio function status return.
Definition: hal_audio.h:1218
int hal_audio_resample_set_config(float in_rate, float out_rate, int is_stereo, int gain)
Configure audio_control resample function settings.
int hal_audio_enc_pdm_dc_offset_cal(int bytes_per_frame, int is_stereo, int num_frames_skip, int num_frames_samp)
Calibrate PDM Encoder DC Offset. Must be called after hal_audio_enc_set_config. Once called...
int hal_audio_decode_start(uint8_t *in_buf, uint16_t buf_size, uint16_t *in_size, void *pv, void(*dec_lmt_callback)(void *pv))
Begin decode audio functionality based on current configuration and input data.
Error, HW GPIO configuration error.
Definition: hal_audio.h:1234
int hal_audio_encode_process(uint8_t *out_buf, uint32_t buf_sz, uint16_t *in_size)
Request encoded data.
int hal_audio_resample_close(void)
Clean-up resample functionality.
Error, Audio interrupt trigger.
Definition: hal_audio.h:1236
int hal_audio_dec_close(void)
Clean-up decode functionality.
int hal_audio_encode_start(void *pv, void(*enc_lmt_callback)(void *))
Begin encode audio functionality based on current configuration.
int hal_audio_enc_close(void)
Clean-up encode functionality.
int hal_audio_resample_stop(void)
Stop resample audio functionality.
Error, current operation block.
Definition: hal_audio.h:1230
int hal_audio_dec_set_predict_endianness(int is_little_end)
Configure decode frame header endianness.
int hal_audio_dec_open(void)
Initialize decode functionality.
Error, AUDIO driver not initialized.
Definition: hal_audio.h:1222
int hal_audio_resample_process(uint32_t *in_buf, uint16_t *in_size, uint32_t *out_buf)
Execute resample audio functionality based on current configuration and input data.
int hal_audio_decode_process(uint8_t *in_buf, uint16_t buf_size, uint16_t *in_size)
Provide audio hardware with additional encoded data to be decoded.
Error, invalid AUDIO parameter.
Definition: hal_audio.h:1228
int hal_audio_resample_open(void)
Initialize resample functionality.
Error, configuration not initialized.
Definition: hal_audio.h:1232
Error, AUDIO driver already initialized.
Definition: hal_audio.h:1224
Error, AUDIO bad state.
Definition: hal_audio.h:1226
int hal_audio_enc_open(void)
Initialize encode functionality.
int hal_audio_enc_set_predict_endianness(int is_little_end)
Configure encode frame header endianness.