35 #define AES_DATA_BLOCK_OFFSET_INDEX 0x0400 36 #define AES_CONTEXT_BLOCK_OFFSET_INDEX 0x0800 37 #define AES_CONTEXT_MEMORY_BLOCK0_INDEX 0x0000 38 #define AES_CONTEXT_MEMORY_BLOCK1_INDEX 0x0020 39 #define AES_CONTEXT_MEMORY_BLOCK2_INDEX 0x0030 40 #define AES_CONTEXT_MEMORY_BLOCK3_INDEX 0x0040 41 #define AES_CONTEXT_MEMORY_BLOCK4_INDEX 0x0050 43 #define AES_DATA_BASE AES_REG_BASE + AES_DATA_BLOCK_OFFSET_INDEX 44 #define AES_CONTEXT_BASE AES_REG_BASE + AES_CONTEXT_BLOCK_OFFSET_INDEX 45 #define AES_CONTEXT_MEMORY_BLOCK0_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK0_INDEX 46 #define AES_CONTEXT_MEMORY_BLOCK1_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK1_INDEX 47 #define AES_CONTEXT_MEMORY_BLOCK2_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK2_INDEX 48 #define AES_CONTEXT_MEMORY_BLOCK3_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK3_INDEX 49 #define AES_CONTEXT_MEMORY_BLOCK4_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK4_INDEX 51 #define AES_MESSAGE_MEM_SIZE (256) //maximum message memory size 63 AES_ERR_NOT_ENOUGH_BUF = 6,
64 AES_ERR_INVALID_PARAM = 7,
134 static __inline
void aes_set_misc_ctrl_go(
void)
136 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
137 reg |= AES_REG_MISC_CTRL_GO;
138 WR_WORD(AES_REG_MISC_CTRL, reg);
141 static __inline
void aes_clr_misc_ctrl_go(
void)
143 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
144 reg &= ~AES_REG_MISC_CTRL_GO;
145 WR_WORD(AES_REG_MISC_CTRL, reg);
148 static __inline
void aes_set_misc_ctrl(
int mode,
int key_size, uint8_t mac_length)
150 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
153 reg &= ~(AES_REG_MISC_CTRL_MODE);
154 reg |= ((mode & AES_REG_MISC_CTRL_MODE_MASK) << AES_REG_MISC_CTRL_MODE_SHIFT);
157 reg &= ~(AES_REG_MISC_CTRL_KEY_SIZE);
158 reg |= ((key_size & AES_REG_MISC_CTRL_KEY_SIZE_MASK) << AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
161 reg &= ~(AES_REG_MISC_CTRL_MAC_LEN);
162 if (mac_length == 16)
164 reg |= ((mac_length & AES_REG_MISC_CTRL_MAC_LEN_MASK) << AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
166 WR_WORD(AES_REG_MISC_CTRL, reg);
171 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
173 reg |= AES_REG_MISC_CTRL_ENCRYPT;
175 reg &= ~(AES_REG_MISC_CTRL_ENCRYPT);
177 WR_WORD(AES_REG_MISC_CTRL, reg);
182 uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_ENCRYPT) >> 1);
189 static __inline
void aes_set_misc_ctrl_msg_begin(
void)
191 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
192 reg |= AES_REG_MISC_CTRL_MSG_BEGIN;
193 WR_WORD(AES_REG_MISC_CTRL, reg);
196 static __inline
void aes_clr_misc_ctrl_msg_begin(
void)
198 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
199 reg &= ~AES_REG_MISC_CTRL_MSG_BEGIN;
200 WR_WORD(AES_REG_MISC_CTRL, reg);
203 static __inline
void aes_set_misc_ctrl_msg_end(
void)
205 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
206 reg |= AES_REG_MISC_CTRL_MSG_END;
207 WR_WORD(AES_REG_MISC_CTRL, reg);
210 static __inline
void aes_clr_misc_ctrl_msg_end(
void)
212 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
213 reg &= ~AES_REG_MISC_CTRL_MSG_END;
214 WR_WORD(AES_REG_MISC_CTRL, reg);
219 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
220 uint8_t val = (uint8_t)mode;
221 reg &= ~(AES_REG_MISC_CTRL_MODE);
222 reg |= ((val & AES_REG_MISC_CTRL_MODE_MASK) << AES_REG_MISC_CTRL_MODE_SHIFT);
223 WR_WORD(AES_REG_MISC_CTRL, reg);
228 uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_MODE) >> AES_REG_MISC_CTRL_MODE_SHIFT);
243 static __inline
void aes_set_misc_ctrl_mac_len(uint8_t length)
245 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
246 reg &= ~(AES_REG_MISC_CTRL_MAC_LEN);
247 reg |= ((length & AES_REG_MISC_CTRL_MAC_LEN_MASK) << AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
248 WR_WORD(AES_REG_MISC_CTRL, reg);
251 static __inline uint8_t aes_get_misc_ctrl_mac_len(
void)
253 uint8_t len = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_MAC_LEN) >> AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
260 static __inline
void aes_set_misc_ctrl_key_size(
aes_key_size size)
262 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
270 reg &= ~(AES_REG_MISC_CTRL_KEY_SIZE);
271 reg |= ((val & AES_REG_MISC_CTRL_KEY_SIZE_MASK) << AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
272 WR_WORD(AES_REG_MISC_CTRL, reg);
275 static __inline
aes_key_size aes_get_misc_ctrl_key_size(
void)
277 uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_KEY_SIZE) >> AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
286 static __inline
void aes_set_misc_ctrl_str_ctx(
void)
288 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
289 reg |= AES_REG_MISC_CTRL_STR_CTX;
290 WR_WORD(AES_REG_MISC_CTRL, reg);
293 static __inline
void aes_clr_misc_ctrl_str_ctx(
void)
295 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
296 reg &= ~AES_REG_MISC_CTRL_STR_CTX;
297 WR_WORD(AES_REG_MISC_CTRL, reg);
300 static __inline
void aes_set_misc_ctrl_ret_ctx(
void)
302 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
303 reg |= AES_REG_MISC_CTRL_RET_CTX;
304 WR_WORD(AES_REG_MISC_CTRL, reg);
307 static __inline
void aes_clr_misc_ctrl_ret_ctx(
void)
309 uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
310 reg &= ~AES_REG_MISC_CTRL_RET_CTX;
311 WR_WORD(AES_REG_MISC_CTRL, reg);
314 #define AES_CTX_INDEX 0x0000000F 316 #define AES_BLOCK_INDEX 0x00000003 318 #define AES_AAD_LENGTH 0x0000007F 320 static __inline
void aes_set_aad_length(uint32_t length)
322 uint32_t reg = RD_WORD(AES_REG_AAD_LENGTH);
323 reg &= ~(AES_REG_AAD_LENGTH_LENGTH);
324 reg |= (length & AES_REG_AAD_LENGTH_LENGTH_MASK);
325 WR_WORD(AES_REG_AAD_LENGTH, reg);
328 static __inline uint32_t aes_get_aad_length(
void)
330 return (RD_WORD(AES_REG_AAD_LENGTH) & AES_REG_AAD_LENGTH_LENGTH_MASK);
333 #define AES_NUM_BYTES 0x0000007F 335 static __inline
void aes_set_num_bytes(uint32_t num)
337 uint32_t reg = RD_WORD(AES_REG_NUM_BYTES);
338 reg &= ~(AES_REG_NUM_BYTES_NUM_BYTES);
339 reg |= (num & AES_REG_NUM_BYTES_NUM_BYTES_MASK);
340 WR_WORD(AES_REG_NUM_BYTES, reg);
343 static __inline uint32_t aes_get_num_bytes(
void)
345 return (RD_WORD(AES_REG_NUM_BYTES) & AES_REG_NUM_BYTES_NUM_BYTES_MASK);
348 #define AES_NUM_TOTAL_BYTES 0x0000FFFF 350 static __inline
void aes_set_num_total_bytes(uint32_t num)
352 uint32_t reg = RD_WORD(AES_REG_NUM_TOTAL_BYTES);
353 reg &= ~(AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES);
354 reg |= (num & AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES_MASK);
355 WR_WORD(AES_REG_NUM_TOTAL_BYTES, reg);
358 static __inline uint32_t aes_get_num_total_bytes(
void)
360 return (RD_WORD(AES_REG_NUM_TOTAL_BYTES) & AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES_MASK);
363 #define AES_TAG_MSG_ADDR 0x0000003F 365 #define AES_AAD_LEN_TOTAL 0x0000FFFF 367 static __inline
void aes_set_aad_length_total(uint32_t length)
369 uint32_t reg = RD_WORD(AES_REG_AAD_LEN_TOTAL);
370 reg &= ~(AES_REG_AAD_LEN_TOTAL_LEN);
371 reg |= (length & AES_REG_AAD_LEN_TOTAL_LEN_MASK);
372 WR_WORD(AES_REG_AAD_LEN_TOTAL, reg);
375 static __inline uint32_t aes_get_aad_length_total(
void)
377 return (RD_WORD(AES_REG_AAD_LEN_TOTAL) & AES_REG_AAD_LEN_TOTAL_LEN_MASK);
381 #define HASH_REG_OFFSET_INTR 0x00000800UL 382 #define HASH_REG_OFFSET_INTR_EN 0x00000040UL 383 #define HASH_REG_OFFSET_INTR_CLR 0x00000080UL 384 #define HASH_REG_OFFSET_INTR_STATUS 0x00000100UL 386 #define AES_REG_CRYPTO_STATUS (AES_REG_BASE + 0x20) 387 #define AES_REG_CRYPTO_STATUS_INTR_EN 0x001 388 #define AES_REG_CRYPTO_STATUS_INTR_CLR 0x002 389 #define AES_REG_CRYPTO_STATUS_INTR_STATUS 0x004 390 #define AES_REG_CRYPTO_STATUS_INTR_STATUS_SHIFT (2) 391 #define AES_REG_CRYPTO_STATUS_STATUS 0x100 392 #define AES_REG_CRYPTO_STATUS_STATUS_SHIFT (8) 393 #define AES_REG_CRYPTO_STATUS_MAC_VER 0x200 394 #define AES_REG_CRYPTO_STATUS_MAC_VER_SHIFT (9) 396 static __inline
void aes_intr_unmask() {
397 uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
398 reg |= (AES_REG_CRYPTO_STATUS_INTR_EN);
399 WR_WORD(AES_REG_CRYPTO_STATUS, reg);
402 static __inline
void aes_intr_mask() {
403 uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
404 reg &= ~(AES_REG_CRYPTO_STATUS_INTR_EN);
405 WR_WORD(AES_REG_CRYPTO_STATUS, reg);
408 static __inline
void aes_intr_clr() {
409 uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
410 reg |= (AES_REG_CRYPTO_STATUS_INTR_CLR);
411 WR_WORD(AES_REG_CRYPTO_STATUS, reg);
414 static __inline uint8_t aes_get_crypto_status_intr_status() {
415 return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_INTR_STATUS) >> AES_REG_CRYPTO_STATUS_INTR_STATUS_SHIFT);
418 static __inline uint8_t aes_get_crypto_status_status() {
419 return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_STATUS) >> AES_REG_CRYPTO_STATUS_STATUS_SHIFT);
422 static __inline uint8_t aes_get_crypto_status_mac_ver() {
423 return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_MAC_VER) >> AES_REG_CRYPTO_STATUS_MAC_VER_SHIFT);
426 static __inline
void aes_mem_en(
int en)
429 WR_WORD(GLOBAL_REG_AES_ECC_MEM_SEL, GLOBAL_REG_AES_ECC_MEM_SEL_CTL_AES_ECC_MEM_SEL);
431 WR_WORD(GLOBAL_REG_AES_ECC_MEM_SEL, GLOBAL_REG_AES_ECC_MEM_SEL_DEFAULT);
492 int hal_aes_encrypt(
const uint8_t *input, uint32_t length, uint8_t *output,
bool end);
522 int hal_aes_decrypt(
const uint8_t *input, uint32_t length, uint8_t *output,
bool end);
AES decryption.
Definition: hal_aes.h:72
AES 256-bit key size.
Definition: hal_aes.h:94
AES CTR mode (Counter mode), as defined in NIST Special Publication 800-38A.
Definition: hal_aes.h:81
aes_crypto_type
AES cryptography type.
Definition: hal_aes.h:70
uint8_t * key2
Definition: hal_aes.h:118
AES F8 mode, as defined in RFC 3711.
Definition: hal_aes.h:85
Error, ECC using the HW memory, ECC and AES share the same HW memory.
Definition: hal_aes.h:62
AES CCM mode (Counter with CBC-MAC mode), as defined in NIST Special Publication 800-38C.
Definition: hal_aes.h:82
void hal_aes_set_aad_length(uint32_t length)
Set the AAD data length, CCM mode only. Must be multiple of 16 bytes.
Error, MAC verification failure.
Definition: hal_aes.h:61
AES cryptography configuration structure.
Definition: hal_aes.h:111
No errors, good status.
Definition: hal_aes.h:57
uint8_t * salt
Definition: hal_aes.h:116
Error, AES bad state.
Definition: hal_aes.h:60
uint8_t mac_length
Definition: hal_aes.h:128
aes_key_size
AES key size.
Definition: hal_aes.h:91
aes_crypto_mode mode
Definition: hal_aes.h:112
uint8_t * iv
Definition: hal_aes.h:124
void hal_aes_get_encrypt_mac(uint8_t *mac, uint32_t buf_sz)
Get the MAC result after encryption, only for CMAC, CCM and XCBC modes.
int hal_aes_config(aes_cfg_t *cfg)
AES cryptography configuration function, call this function before calling hal_aes_encrypt/hal_aes_de...
const uint8_t * key
Definition: hal_aes.h:114
aes_crypto_mode
AES cryptography mode.
Definition: hal_aes.h:78
uint8_t * ctr_blk
Definition: hal_aes.h:122
AES encryption.
Definition: hal_aes.h:71
AES 128-bit key size.
Definition: hal_aes.h:92
int hal_aes_decrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end)
Do the decrypt process.
Error, AES driver not initialized.
Definition: hal_aes.h:58
int hal_aes_close(void)
De-Initialize AES driver for power management and interrupt purposes.
aes_key_size key_size
Definition: hal_aes.h:113
int hal_aes_open(void)
Initialize AES driver for power management and interrupt purposes.
AES XCBC mode (3-key variant, as specified in Rogaway and BlackĄ¯s NIST submission) ...
Definition: hal_aes.h:84
AES CBC mode (Cipher Block Chaining mode), as defined in NIST Special Publication 800-38A...
Definition: hal_aes.h:80
aes_crypto_status
AES function status return.
Definition: hal_aes.h:56
const uint8_t * mac
Definition: hal_aes.h:127
int hal_aes_encrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end)
Do the encrypt process.
int hal_aes_is_open(void)
Ecc and Aes shared the same HW memory. This is to inform Ecc that Aes currently is using the HW memor...
uint8_t * key3
Definition: hal_aes.h:123
AES ECB mode (Electronic Codebook mode), as defined in NIST Special Publication 800-38A.
Definition: hal_aes.h:79
AES 192-bit key size.
Definition: hal_aes.h:93
Error, AES driver already initialized.
Definition: hal_aes.h:59
AES CMAC mode (Cipher-based Message Authentication Code mode), as defined in NIST Special Publication...
Definition: hal_aes.h:83
uint16_t total_msg_length
Definition: hal_aes.h:130
void hal_aes_get_iv(uint8_t iv[16])
Get the IV result after encryption, only for CBC and F8 modes.