InPlay API
hal_aes.h
1 
13 #ifndef HAL_AES_H
14 #define HAL_AES_H
15 
25 #include <stdint.h>
26 #include <stdbool.h>
27 #include "in_mmap.h"
28 
29 /*
30  ****************************************************************************************
31  * DEFINES
32  ****************************************************************************************
33  */
34 
35 #define AES_DATA_BLOCK_OFFSET_INDEX 0x0400
36 #define AES_CONTEXT_BLOCK_OFFSET_INDEX 0x0800
37 #define AES_CONTEXT_MEMORY_BLOCK0_INDEX 0x0000
38 #define AES_CONTEXT_MEMORY_BLOCK1_INDEX 0x0020
39 #define AES_CONTEXT_MEMORY_BLOCK2_INDEX 0x0030
40 #define AES_CONTEXT_MEMORY_BLOCK3_INDEX 0x0040
41 #define AES_CONTEXT_MEMORY_BLOCK4_INDEX 0x0050
42 
43 #define AES_DATA_BASE AES_REG_BASE + AES_DATA_BLOCK_OFFSET_INDEX
44 #define AES_CONTEXT_BASE AES_REG_BASE + AES_CONTEXT_BLOCK_OFFSET_INDEX
45 #define AES_CONTEXT_MEMORY_BLOCK0_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK0_INDEX
46 #define AES_CONTEXT_MEMORY_BLOCK1_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK1_INDEX
47 #define AES_CONTEXT_MEMORY_BLOCK2_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK2_INDEX
48 #define AES_CONTEXT_MEMORY_BLOCK3_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK3_INDEX
49 #define AES_CONTEXT_MEMORY_BLOCK4_BASE AES_CONTEXT_BASE + AES_CONTEXT_MEMORY_BLOCK4_INDEX
50 
51 #define AES_MESSAGE_MEM_SIZE (256) //maximum message memory size
52 
56 typedef enum {
57  AES_ERR_OK = 0,
63  AES_ERR_NOT_ENOUGH_BUF = 6,
64  AES_ERR_INVALID_PARAM = 7,
66 
70 typedef enum {
74 
78 typedef enum {
87 
91 typedef enum {
95 } aes_key_size ;
96 
111 typedef struct {
114  const uint8_t *key;
115  union {
116  uint8_t *salt;
118  uint8_t *key2;
119  } u1;
120 
121  union {
122  uint8_t *ctr_blk;
123  uint8_t *key3;
124  uint8_t *iv;
125  } u2;
126 
127  const uint8_t *mac;
128  uint8_t mac_length;
130  uint16_t total_msg_length;
132 } aes_cfg_t;
133 
134 static __inline void aes_set_misc_ctrl_go(void)
135 {
136  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
137  reg |= AES_REG_MISC_CTRL_GO;
138  WR_WORD(AES_REG_MISC_CTRL, reg);
139 }
140 
141 static __inline void aes_clr_misc_ctrl_go(void)
142 {
143  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
144  reg &= ~AES_REG_MISC_CTRL_GO;
145  WR_WORD(AES_REG_MISC_CTRL, reg);
146 }
147 
148 static __inline void aes_set_misc_ctrl(int mode, int key_size, uint8_t mac_length)
149 {
150  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
151 
153  reg &= ~(AES_REG_MISC_CTRL_MODE);
154  reg |= ((mode & AES_REG_MISC_CTRL_MODE_MASK) << AES_REG_MISC_CTRL_MODE_SHIFT);
155 
157  reg &= ~(AES_REG_MISC_CTRL_KEY_SIZE);
158  reg |= ((key_size & AES_REG_MISC_CTRL_KEY_SIZE_MASK) << AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
159 
161  reg &= ~(AES_REG_MISC_CTRL_MAC_LEN);
162  if (mac_length == 16)
163  mac_length = 0;
164  reg |= ((mac_length & AES_REG_MISC_CTRL_MAC_LEN_MASK) << AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
165 
166  WR_WORD(AES_REG_MISC_CTRL, reg);
167 }
168 
169 static __inline void aes_set_misc_ctrl_type(aes_crypto_type type)
170 {
171  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
172  if(type == AES_CRYPTO_TYPE_ENCRYPT)
173  reg |= AES_REG_MISC_CTRL_ENCRYPT;
174  else
175  reg &= ~(AES_REG_MISC_CTRL_ENCRYPT);
176 
177  WR_WORD(AES_REG_MISC_CTRL, reg);
178 }
179 
180 static __inline aes_crypto_type aes_get_misc_ctrl_type(void)
181 {
182  uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_ENCRYPT) >> 1);
183  if(reg)
185  else
187 }
188 
189 static __inline void aes_set_misc_ctrl_msg_begin(void)
190 {
191  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
192  reg |= AES_REG_MISC_CTRL_MSG_BEGIN;
193  WR_WORD(AES_REG_MISC_CTRL, reg);
194 }
195 
196 static __inline void aes_clr_misc_ctrl_msg_begin(void)
197 {
198  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
199  reg &= ~AES_REG_MISC_CTRL_MSG_BEGIN;
200  WR_WORD(AES_REG_MISC_CTRL, reg);
201 }
202 
203 static __inline void aes_set_misc_ctrl_msg_end(void)
204 {
205  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
206  reg |= AES_REG_MISC_CTRL_MSG_END;
207  WR_WORD(AES_REG_MISC_CTRL, reg);
208 }
209 
210 static __inline void aes_clr_misc_ctrl_msg_end(void)
211 {
212  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
213  reg &= ~AES_REG_MISC_CTRL_MSG_END;
214  WR_WORD(AES_REG_MISC_CTRL, reg);
215 }
216 
217 static __inline void aes_set_misc_ctrl_mode(aes_crypto_mode mode)
218 {
219  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
220  uint8_t val = (uint8_t)mode;
221  reg &= ~(AES_REG_MISC_CTRL_MODE);
222  reg |= ((val & AES_REG_MISC_CTRL_MODE_MASK) << AES_REG_MISC_CTRL_MODE_SHIFT);
223  WR_WORD(AES_REG_MISC_CTRL, reg);
224 }
225 
226 static __inline aes_crypto_mode aes_get_misc_ctrl_mode(void)
227 {
228  uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_MODE) >> AES_REG_MISC_CTRL_MODE_SHIFT);
229  if(reg == 0)
230  return AES_CRYPTO_MODE_ECB;
231  else if(reg == 1)
232  return AES_CRYPTO_MODE_CBC;
233  else if(reg == 2)
234  return AES_CRYPTO_MODE_CTR;
235  else if(reg == 3)
236  return AES_CRYPTO_MODE_CCM;
237  else if(reg == 4)
238  return AES_CRYPTO_MODE_CMAC;
239  else
240  return AES_CRYPTO_MODE_F8;
241 }
242 
243 static __inline void aes_set_misc_ctrl_mac_len(uint8_t length)
244 {
245  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
246  reg &= ~(AES_REG_MISC_CTRL_MAC_LEN);
247  reg |= ((length & AES_REG_MISC_CTRL_MAC_LEN_MASK) << AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
248  WR_WORD(AES_REG_MISC_CTRL, reg);
249 }
250 
251 static __inline uint8_t aes_get_misc_ctrl_mac_len(void)
252 {
253  uint8_t len = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_MAC_LEN) >> AES_REG_MISC_CTRL_MAC_LEN_SHIFT);
254  if(len == 0)
255  return 16;
256  else
257  return len;
258 }
259 
260 static __inline void aes_set_misc_ctrl_key_size(aes_key_size size)
261 {
262  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
263  uint8_t val;
264  if(size == AES_KEY_SIZE_128)
265  val = 0;
266  else if(size == AES_KEY_SIZE_192)
267  val = 1;
268  else if(size == AES_KEY_SIZE_256)
269  val = 2;
270  reg &= ~(AES_REG_MISC_CTRL_KEY_SIZE);
271  reg |= ((val & AES_REG_MISC_CTRL_KEY_SIZE_MASK) << AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
272  WR_WORD(AES_REG_MISC_CTRL, reg);
273 }
274 
275 static __inline aes_key_size aes_get_misc_ctrl_key_size(void)
276 {
277  uint32_t reg = ((RD_WORD(AES_REG_MISC_CTRL) & AES_REG_MISC_CTRL_KEY_SIZE) >> AES_REG_MISC_CTRL_KEY_SIZE_SHIFT);
278  if(reg == 0)
279  return AES_KEY_SIZE_128;
280  else if(reg == 1)
281  return AES_KEY_SIZE_192;
282  else
283  return AES_KEY_SIZE_256;
284 }
285 
286 static __inline void aes_set_misc_ctrl_str_ctx(void)
287 {
288  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
289  reg |= AES_REG_MISC_CTRL_STR_CTX;
290  WR_WORD(AES_REG_MISC_CTRL, reg);
291 }
292 
293 static __inline void aes_clr_misc_ctrl_str_ctx(void)
294 {
295  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
296  reg &= ~AES_REG_MISC_CTRL_STR_CTX;
297  WR_WORD(AES_REG_MISC_CTRL, reg);
298 }
299 
300 static __inline void aes_set_misc_ctrl_ret_ctx(void)
301 {
302  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
303  reg |= AES_REG_MISC_CTRL_RET_CTX;
304  WR_WORD(AES_REG_MISC_CTRL, reg);
305 }
306 
307 static __inline void aes_clr_misc_ctrl_ret_ctx(void)
308 {
309  uint32_t reg = RD_WORD(AES_REG_MISC_CTRL);
310  reg &= ~AES_REG_MISC_CTRL_RET_CTX;
311  WR_WORD(AES_REG_MISC_CTRL, reg);
312 }
313 
314 #define AES_CTX_INDEX 0x0000000F
315 
316 #define AES_BLOCK_INDEX 0x00000003
317 
318 #define AES_AAD_LENGTH 0x0000007F
319 
320 static __inline void aes_set_aad_length(uint32_t length)
321 {
322  uint32_t reg = RD_WORD(AES_REG_AAD_LENGTH);
323  reg &= ~(AES_REG_AAD_LENGTH_LENGTH);
324  reg |= (length & AES_REG_AAD_LENGTH_LENGTH_MASK);
325  WR_WORD(AES_REG_AAD_LENGTH, reg);
326 }
327 
328 static __inline uint32_t aes_get_aad_length(void)
329 {
330  return (RD_WORD(AES_REG_AAD_LENGTH) & AES_REG_AAD_LENGTH_LENGTH_MASK);
331 }
332 
333 #define AES_NUM_BYTES 0x0000007F
334 
335 static __inline void aes_set_num_bytes(uint32_t num)
336 {
337  uint32_t reg = RD_WORD(AES_REG_NUM_BYTES);
338  reg &= ~(AES_REG_NUM_BYTES_NUM_BYTES);
339  reg |= (num & AES_REG_NUM_BYTES_NUM_BYTES_MASK);
340  WR_WORD(AES_REG_NUM_BYTES, reg);
341 }
342 
343 static __inline uint32_t aes_get_num_bytes(void)
344 {
345  return (RD_WORD(AES_REG_NUM_BYTES) & AES_REG_NUM_BYTES_NUM_BYTES_MASK);
346 }
347 
348 #define AES_NUM_TOTAL_BYTES 0x0000FFFF
349 
350 static __inline void aes_set_num_total_bytes(uint32_t num)
351 {
352  uint32_t reg = RD_WORD(AES_REG_NUM_TOTAL_BYTES);
353  reg &= ~(AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES);
354  reg |= (num & AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES_MASK);
355  WR_WORD(AES_REG_NUM_TOTAL_BYTES, reg);
356 }
357 
358 static __inline uint32_t aes_get_num_total_bytes(void)
359 {
360  return (RD_WORD(AES_REG_NUM_TOTAL_BYTES) & AES_REG_NUM_TOTAL_BYTES_NUM_TOTAL_BYTES_MASK);
361 }
362 
363 #define AES_TAG_MSG_ADDR 0x0000003F
364 
365 #define AES_AAD_LEN_TOTAL 0x0000FFFF
366 
367 static __inline void aes_set_aad_length_total(uint32_t length)
368 {
369  uint32_t reg = RD_WORD(AES_REG_AAD_LEN_TOTAL);
370  reg &= ~(AES_REG_AAD_LEN_TOTAL_LEN);
371  reg |= (length & AES_REG_AAD_LEN_TOTAL_LEN_MASK);
372  WR_WORD(AES_REG_AAD_LEN_TOTAL, reg);
373 }
374 
375 static __inline uint32_t aes_get_aad_length_total(void)
376 {
377  return (RD_WORD(AES_REG_AAD_LEN_TOTAL) & AES_REG_AAD_LEN_TOTAL_LEN_MASK);
378 }
379 
380 
381 #define HASH_REG_OFFSET_INTR 0x00000800UL
382 #define HASH_REG_OFFSET_INTR_EN 0x00000040UL
383 #define HASH_REG_OFFSET_INTR_CLR 0x00000080UL
384 #define HASH_REG_OFFSET_INTR_STATUS 0x00000100UL
385 
386 #define AES_REG_CRYPTO_STATUS (AES_REG_BASE + 0x20)
387 #define AES_REG_CRYPTO_STATUS_INTR_EN 0x001
388 #define AES_REG_CRYPTO_STATUS_INTR_CLR 0x002
389 #define AES_REG_CRYPTO_STATUS_INTR_STATUS 0x004
390 #define AES_REG_CRYPTO_STATUS_INTR_STATUS_SHIFT (2)
391 #define AES_REG_CRYPTO_STATUS_STATUS 0x100
392 #define AES_REG_CRYPTO_STATUS_STATUS_SHIFT (8)
393 #define AES_REG_CRYPTO_STATUS_MAC_VER 0x200
394 #define AES_REG_CRYPTO_STATUS_MAC_VER_SHIFT (9)
395 
396 static __inline void aes_intr_unmask() {
397  uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
398  reg |= (AES_REG_CRYPTO_STATUS_INTR_EN);
399  WR_WORD(AES_REG_CRYPTO_STATUS, reg);
400 }
401 
402 static __inline void aes_intr_mask() {
403  uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
404  reg &= ~(AES_REG_CRYPTO_STATUS_INTR_EN);
405  WR_WORD(AES_REG_CRYPTO_STATUS, reg);
406 }
407 
408 static __inline void aes_intr_clr() {
409  uint32_t reg = RD_WORD(AES_REG_CRYPTO_STATUS);
410  reg |= (AES_REG_CRYPTO_STATUS_INTR_CLR);
411  WR_WORD(AES_REG_CRYPTO_STATUS, reg);
412 }
413 
414 static __inline uint8_t aes_get_crypto_status_intr_status() {
415  return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_INTR_STATUS) >> AES_REG_CRYPTO_STATUS_INTR_STATUS_SHIFT);
416 }
417 
418 static __inline uint8_t aes_get_crypto_status_status() {
419  return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_STATUS) >> AES_REG_CRYPTO_STATUS_STATUS_SHIFT);
420 }
421 
422 static __inline uint8_t aes_get_crypto_status_mac_ver() {
423  return ((RD_WORD(AES_REG_CRYPTO_STATUS) & AES_REG_CRYPTO_STATUS_MAC_VER) >> AES_REG_CRYPTO_STATUS_MAC_VER_SHIFT);
424 }
425 
426 static __inline void aes_mem_en(int en)
427 {
428  if (en)
429  WR_WORD(GLOBAL_REG_AES_ECC_MEM_SEL, GLOBAL_REG_AES_ECC_MEM_SEL_CTL_AES_ECC_MEM_SEL);
430  else
431  WR_WORD(GLOBAL_REG_AES_ECC_MEM_SEL, GLOBAL_REG_AES_ECC_MEM_SEL_DEFAULT);
432 
433 }
434 
442 int hal_aes_open(void);
443 
451 int hal_aes_close(void);
452 
460 int hal_aes_is_open(void);
461 
469 int hal_aes_config(aes_cfg_t *cfg);
470 
478 void hal_aes_set_aad_length(uint32_t length);
479 
492 int hal_aes_encrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end);
493 
500 void hal_aes_get_encrypt_mac(uint8_t *mac, uint32_t buf_sz);
501 
507 void hal_aes_get_iv(uint8_t iv[16]);
508 
522 int hal_aes_decrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end);
523 
525 #endif
526 
AES decryption.
Definition: hal_aes.h:72
AES 256-bit key size.
Definition: hal_aes.h:94
AES CTR mode (Counter mode), as defined in NIST Special Publication 800-38A.
Definition: hal_aes.h:81
aes_crypto_type
AES cryptography type.
Definition: hal_aes.h:70
uint8_t * key2
Definition: hal_aes.h:118
AES F8 mode, as defined in RFC 3711.
Definition: hal_aes.h:85
Error, ECC using the HW memory, ECC and AES share the same HW memory.
Definition: hal_aes.h:62
AES CCM mode (Counter with CBC-MAC mode), as defined in NIST Special Publication 800-38C.
Definition: hal_aes.h:82
void hal_aes_set_aad_length(uint32_t length)
Set the AAD data length, CCM mode only. Must be multiple of 16 bytes.
Error, MAC verification failure.
Definition: hal_aes.h:61
AES cryptography configuration structure.
Definition: hal_aes.h:111
No errors, good status.
Definition: hal_aes.h:57
uint8_t * salt
Definition: hal_aes.h:116
Error, AES bad state.
Definition: hal_aes.h:60
uint8_t mac_length
Definition: hal_aes.h:128
aes_key_size
AES key size.
Definition: hal_aes.h:91
aes_crypto_mode mode
Definition: hal_aes.h:112
uint8_t * iv
Definition: hal_aes.h:124
void hal_aes_get_encrypt_mac(uint8_t *mac, uint32_t buf_sz)
Get the MAC result after encryption, only for CMAC, CCM and XCBC modes.
int hal_aes_config(aes_cfg_t *cfg)
AES cryptography configuration function, call this function before calling hal_aes_encrypt/hal_aes_de...
const uint8_t * key
Definition: hal_aes.h:114
aes_crypto_mode
AES cryptography mode.
Definition: hal_aes.h:78
uint8_t * ctr_blk
Definition: hal_aes.h:122
AES encryption.
Definition: hal_aes.h:71
AES 128-bit key size.
Definition: hal_aes.h:92
int hal_aes_decrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end)
Do the decrypt process.
Error, AES driver not initialized.
Definition: hal_aes.h:58
int hal_aes_close(void)
De-Initialize AES driver for power management and interrupt purposes.
aes_key_size key_size
Definition: hal_aes.h:113
int hal_aes_open(void)
Initialize AES driver for power management and interrupt purposes.
AES XCBC mode (3-key variant, as specified in Rogaway and BlackĄ¯s NIST submission) ...
Definition: hal_aes.h:84
AES CBC mode (Cipher Block Chaining mode), as defined in NIST Special Publication 800-38A...
Definition: hal_aes.h:80
aes_crypto_status
AES function status return.
Definition: hal_aes.h:56
const uint8_t * mac
Definition: hal_aes.h:127
int hal_aes_encrypt(const uint8_t *input, uint32_t length, uint8_t *output, bool end)
Do the encrypt process.
int hal_aes_is_open(void)
Ecc and Aes shared the same HW memory. This is to inform Ecc that Aes currently is using the HW memor...
uint8_t * key3
Definition: hal_aes.h:123
AES ECB mode (Electronic Codebook mode), as defined in NIST Special Publication 800-38A.
Definition: hal_aes.h:79
AES 192-bit key size.
Definition: hal_aes.h:93
Error, AES driver already initialized.
Definition: hal_aes.h:59
AES CMAC mode (Cipher-based Message Authentication Code mode), as defined in NIST Special Publication...
Definition: hal_aes.h:83
uint16_t total_msg_length
Definition: hal_aes.h:130
void hal_aes_get_iv(uint8_t iv[16])
Get the IV result after encryption, only for CBC and F8 modes.