hal_adc.h

#ifndef HAL_ADC
#define HAL_ADC

#include <stdint.h>
#include "in_mmap.h"
#include "in_compile.h"
#include "./hal/hal_power.h"

#define ADC_INTR_SAMPLE_DONE 0x00000001UL
#define ADC_INTR_FIFO_FULL   0x00000002UL
#define ADC_INTR_FIFO_EMPTY   0x00000004UL
#define ADC_INTR_FIFO_ALMOST_FULL   0x00000008UL

#define ADC_CH_VBAT ADC_CH14
#define ADC_CH_TEMP ADC_CH15
#define ADC_EFUSE_SAMPLES   (16) //c0: 32, e0: 16

#define ADC_VBAT_SAMPLES     (16)
#define ADC_TEMP_SAMPLES     (16)
#define ADC_CHX_SAMPLES     (16)

#define ADC_SAMPLE_RETRY    (1000)

enum adc_ch{
    ADC_CH0 = 0, 
    ADC_CH1,   
    ADC_CH2,   
    ADC_CH3,   
    ADC_CH4,   
    ADC_CH5,   
    ADC_CH6,   
    ADC_CH7,   
    ADC_CH8,   
    ADC_CH9,   
    ADC_CH10 = 10,  
    ADC_CH11,  
    ADC_CH12,  
    ADC_CH13,  
    ADC_CH14 = 14,  
    ADC_CH15 = 15,  
    ADC_CH_MAX = 16,
};
enum adc_error {
    ADC_ERR_OK = 0, 
    ADC_ERR_INVALID_PARAM = -1,
    ADC_ERR_EFUSE = -2,
    ADC_ERR_SMEM = -3,
    ADC_ERR_HW = -4,
    ADC_ERR_TIMEOUT = -5,
    ADC_ERR_SEMA = -6,
    ADC_ERR_INIT = -7,
    
};
typedef enum adc_vref {
    ADC_VREF_1P0 = 0, 
    ADC_VREF_1P5 = 1, 
}adc_vref_t ;
typedef struct {
    int vref;
    int irq_prio; 
    void *arg;  
    void (*cb)(void *arg); 
} adc_init_t;


typedef struct adc_ch_timing {
    uint8_t sample_dly;
    uint8_t sample_dly_en;
    uint8_t capture_clk_half_duration;
    uint8_t num_cap_clk;
} adc_ch_timing_t;


static INLINE uint32_t adc_intr_status(void)
{
    return RD_WORD(SADCCTRL_REG_INTR_STATUS);
}
static INLINE uint32_t adc_intr_mask_status(void)
{
    return RD_WORD(SADCCTRL_REG_INTR_MASK_STATUS);
}
static INLINE void adc_intr_clear(uint32_t reg)
{
    WR_WORD(SADCCTRL_REG_INTR_CLEAR, reg);
}
static INLINE void adc_intr_set(uint32_t reg)
{
    WR_WORD(SADCCTRL_REG_INTR_SET, reg);
}
static INLINE void adc_intr_mask_clear(uint32_t reg)
{
    WR_WORD(SADCCTRL_REG_INTR_MASK_CLEAR, reg);
}
static INLINE void adc_intr_mask_set(uint32_t reg)
{
    WR_WORD(SADCCTRL_REG_INTR_MASK_SET, reg);
}


static INLINE void adc_enable(void)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    reg |= SADCCTRL_REG_MISC_CTRL_CTL_ENABLE;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}
static INLINE void adc_disable(void)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    reg &= ~SADCCTRL_REG_MISC_CTRL_CTL_ENABLE;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}
static INLINE void adc_start(void)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    reg |= SADCCTRL_REG_MISC_CTRL_CTL_START;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}
static INLINE void adc_stop(void)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    //WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
    reg |= SADCCTRL_REG_MISC_CTRL_CTL_END;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}
static INLINE void adc_reset_interrupt(void)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    //WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
    reg |= SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}
static INLINE void adc_use_ana_data_valid(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    if (0 == val)
        reg &= ~SADCCTRL_REG_MISC_CTRL_CTL_USE_ANA_DATA_VALID;
    else
        reg |= SADCCTRL_REG_MISC_CTRL_CTL_USE_ANA_DATA_VALID;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}

static INLINE void adc_en_always_on(uint8_t en)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    if (0 == en)
        reg &= ~SADCCTRL_REG_MISC_CTRL_CTL_ENABLE_ALWAYS_ON;
    else
        reg |= SADCCTRL_REG_MISC_CTRL_CTL_ENABLE_ALWAYS_ON;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}

static INLINE void adc_num_sample(uint16_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_MISC_CTRL);
    reg &= ~(SADCCTRL_REG_MISC_CTRL_CTL_START|SADCCTRL_REG_MISC_CTRL_CTL_END|SADCCTRL_REG_MISC_CTRL_CTL_RST_INTRCTRL);
    reg &= ~SADCCTRL_REG_MISC_CTRL_CTL_NUM_SAMPLES;
    reg |= val<<16;
    WR_WORD(SADCCTRL_REG_MISC_CTRL, reg);
}


static INLINE void adc_set_ch_en(uint16_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL);
    reg &= ~SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_CH_EN;
    reg |= val;
    WR_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL, reg);
}
static INLINE uint32_t adc_get_ch_en(void)
{
    return RD_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL) & SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_CH_EN;
}

static INLINE void adc_sample_grp_intv(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL);
    reg &= ~SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_SAMPLE_GRP_INTERVAL;
    reg |= val << SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_SAMPLE_GRP_INTERVAL_SHIFT;
    WR_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL, reg);
}
static INLINE void adc_disable_grp_intv(uint8_t disable)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL);
    if (0 == disable) 
        reg &= ~SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_DISABLE_BETWEEN_GRP;
    else 
        reg |= SADCCTRL_REG_CHANNEL_EN_CTRL_CTL_DISABLE_BETWEEN_GRP;
    WR_WORD(SADCCTRL_REG_CHANNEL_EN_CTRL, reg);
}

static INLINE void adc_en2start_delay(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL);
    reg &= ~SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_EN2START_DELAY;
    reg |= val & SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_EN2START_DELAY_MASK;
    WR_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL, reg);
}
static INLINE void adc_ch2start_delay(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL);
    reg &= ~SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CH2START_DLY_M1;
    reg |= (val& SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CH2START_DLY_M1_MASK) << SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CH2START_DLY_M1_SHIFT;
    WR_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL, reg);
}

static INLINE void adc_conv_clk_half_duration(uint8_t val) {
    uint32_t reg = RD_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL);
    reg &= ~SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CONV_CLK_HLF_DUR;
    reg |= (val& SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CONV_CLK_HLF_DUR_MASK) << SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_CONV_CLK_HLF_DUR_SHIFT;
    WR_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL, reg);
}
static INLINE void adc_start_to_capture_offset(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL);
    reg &= ~SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_START_TO_CLK_OFFSET;
    reg |= (val & SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_START_TO_CLK_OFFSET_MASK) << SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_START_TO_CLK_OFFSET_SHIFT;
    WR_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL, reg);
}
static INLINE void adc_ignore_num_clk_before_ready(uint8_t n)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL);
    reg &= ~SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_IGNORE_RDY_NUM_CLK;
    reg |= (n & SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_IGNORE_RDY_NUM_CLK_MASK) << SADCCTRL_REG_SAMPLE_TIMING_CTRL_CTL_IGNORE_RDY_NUM_CLK_SHIFT;
    WR_WORD(SADCCTRL_REG_SAMPLE_TIMING_CTRL, reg);
}

static INLINE void adc_fifo_size(uint16_t reg)
{
    WR_WORD(SADCCTRL_REG_FIFO_CTRL, reg);
}
static INLINE void adc_fifo_almost_full(uint16_t reg)
{
    WR_WORD(SADCCTRL_REG_FIFO_ALMOST_FULL_CTRL, reg);
}

static INLINE uint8_t adc_cur_ch()
{
    return RD_WORD(SADCCTRL_REG_STATUS)&SADCCTRL_REG_STATUS_STS_CURR_CH;
}
static INLINE uint16_t adc_fifo_cnt()
{
    return (RD_WORD(SADCCTRL_REG_STATUS)&SADCCTRL_REG_STATUS_STS_FIFO_CNT)>>4;
}
static INLINE uint8_t adc_fifo_data_ready()
{
    return (RD_WORD(SADCCTRL_REG_STATUS)&SADCCTRL_REG_STATUS_STS_FIFO_RDATA_RDY) >> 31u;
}

static INLINE uint16_t adc_status2_curr_grp_cnt_get(void) {
    return RD_WORD(SADCCTRL_REG_STATUS2)&SADCCTRL_REG_STATUS2_STS_CURR_GRP_CNT_MASK;
}

static INLINE uint16_t adc_fifo_data()
{
    return RD_WORD(SADCCTRL_REG_FIFO_VAL);
}

static INLINE void adc_force_enable()
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_FORCE_CTRL);
    reg |= SADCCTRL_REG_FORCE_CTRL_CTL_FORCE_EN;
    WR_WORD(SADCCTRL_REG_FORCE_CTRL, reg);    
}

static INLINE void adc_force_disable()
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_FORCE_CTRL);
    reg &= ~SADCCTRL_REG_FORCE_CTRL_CTL_FORCE_EN;
    WR_WORD(SADCCTRL_REG_FORCE_CTRL, reg);    
}

static INLINE void adc_force_ch(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_FORCE_CTRL);
    reg &= ~SADCCTRL_REG_FORCE_CTRL_CTL_FORCE_CH;
    reg |= (val & SADCCTRL_REG_FORCE_CTRL_CTL_FORCE_CH_MASK) << SADCCTRL_REG_FORCE_CTRL_CTL_FORCE_CH_SHIFT;
    WR_WORD(SADCCTRL_REG_FORCE_CTRL, reg);    
}

static INLINE uint8_t adc_sts_curr_adc_data_valid(void)
{
    return (RD_WORD(SADCCTRL_REG_FORCE_CTRL) & SADCCTRL_REG_FORCE_CTRL_STS_CURR_ADC_DATA_VALID)>>31u;
}

static INLINE void adc_force_start(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_FORCE_CTRL_START);
    if (0 == val)
        reg &= ~SADCCTRL_REG_FORCE_CTRL_START_CTL_FORCE_START;
    else
        reg |= SADCCTRL_REG_FORCE_CTRL_START_CTL_FORCE_START;
    WR_WORD(SADCCTRL_REG_FORCE_CTRL_START, reg);    
}

static INLINE uint16_t adc_cur_adc_val()
{
    return RD_WORD(SADCCTRL_REG_CURR_ADC_VAL) & SADCCTRL_REG_CURR_ADC_VAL_STS_CUR_ADC_VAL_MASK;
}

static INLINE uint16_t adc_force_adc_val()
{
    return (RD_WORD(SADCCTRL_REG_CURR_ADC_VAL) & SADCCTRL_REG_CURR_ADC_VAL_STS_FORCE_ADC_VAL) >> SADCCTRL_REG_CURR_ADC_VAL_STS_FORCE_ADC_VAL_SHIFT;
}


#define ADC_REF_SEL_MASK 0x000000E0UL
// #define ADC_REF_V1P0  0
// #define ADC_REF_VBAT_DIV2  1
// #define ADC_REF_CH0 2
// #define ADC_REF_CH2 3
// #define ADC_REF_CH4 4
// #define ADC_REF_CH6 5
// #define ADC_REF_CH8 6
// #define ADC_REF_CH10 7



static INLINE void adc_ref_sel(int val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3);
    if (val == 0)
        reg &= ~(1<<24);
    else
        reg |= 1<<24;
    WR_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3, reg);
}
static INLINE void adc_ref_code(uint32_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3);
    reg &= ~(0x1F<<19);
    reg |= (val&0x1F)<<19;
    WR_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3, reg);
}
#define ADC_CH_SEL_MASK 0x10UL 
static INLINE void adc_ch_sel(uint8_t en, uint32_t ch)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3);
    if (1 != en) {
        reg &= ~(1 << 4u);
    } else {
        reg &= ~0x0fu;
        reg |= ch & 0x0fu;
        reg |= (1 << 4u);
    }
    WR_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3, reg);
}

static INLINE void adc_clk_edge_set(uint8_t val)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3);
    if (1 != val) {
        reg &= ~(1 << 8u);
    } else {
        reg |= (1 << 8u);
    }
    WR_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3, reg);
}

static INLINE void adc_offset_cal_en(int en)
{
    uint32_t reg = RD_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3);
    if (en) {
        reg |= 1<<13;
    } else {
        reg &= ~(1<<13);
    }
    WR_WORD(SADCCTRL_REG_SENSOR_ADC_REG1TO3, reg);
}

static INLINE void adc_num_cap_clk(uint32_t addr, uint32_t num)
{
    uint32_t reg = RD_WORD(addr);
    reg &= ~SADCCTRL_REG_CH0_CTL_NUM_CAP_CLK;
    reg |= (num&SADCCTRL_REG_CH0_CTL_NUM_CAP_CLK_MASK)<<SADCCTRL_REG_CH0_CTL_NUM_CAP_CLK_SHIFT;
    WR_WORD(addr, reg);
}

static INLINE void adc_cap_clk_hlf_dur(uint32_t addr, uint32_t num)
{
    uint32_t reg = RD_WORD(addr);
    reg &= ~SADCCTRL_REG_CH0_CTL_CAP_CLK_HLF_DUR;
    reg |= (num&SADCCTRL_REG_CH0_CTL_CAP_CLK_HLF_DUR_MASK)<<SADCCTRL_REG_CH0_CTL_CAP_CLK_HLF_DUR_SHIFT;
    WR_WORD(addr, reg);
}
int hal_adc_open(adc_init_t *init);

void hal_adc_close(void);


int hal_adc_force_mode_enable_ch(int ch);

int hal_adc_force_mode_disable_ch(int ch);

int hal_adc_force_mode_start(int ch, uint16_t* buff, uint16_t sample_num);

int hal_adc_auto_mode_enable_ch(int ch, uint16_t *buf, uint16_t buf_sz);

int hal_adc_auto_mode_disable_ch(int ch);

int hal_adc_auto_mode_config(uint8_t grp_intv);


int hal_adc_auto_mode_start(uint16_t sample_num);


int hal_adc_set_vref(int vref);



int hal_adc_measure_analog_ch(int ch, float vref, float* vc);


float hal_adc_sample_convert(uint16_t adc_val);

float hal_adc_vbat_sample_convert(uint16_t adc_val);

float hal_adc_temp_sample_convert(uint16_t adc_val);

int hal_adc_auto_mode_cap_clk(int ch, uint32_t cap_clk);

int hal_adc_force_mode_cap_clk(uint32_t cap_clk);

int hal_adc_measure_temp(uint16_t sample_num, float *temp);

#endif